[PATCH] D94249: [RISCV] Custom lower ISD::VSCALE.

[Hsiangkai Wang via Phabricator via llvm-commits]

HsiangKai added inline comments.


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Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:653
+    SDValue VScale = DAG.getNode(ISD::SRL, DL, VT, VLENB,
+                                 DAG.getConstant(3, DL, VT));
+    return DAG.getNode(ISD::MUL, DL, VT, VScale, Op.getOperand(0));
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I think we need add comments to explain why we need to shift right 3 bits.


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Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:1854
+  case RISCVISD::READ_VLENB:
+    // We assume VLENB is at least 8 bytes.
+    Known.Zero.setLowBits(3);
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In V specification v1.0, VLEN=128 at least. We could assume VLENB is at least 16 bytes.


Repository:
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  https://reviews.llvm.org/D94249/new/

https://reviews.llvm.org/D94249