[PATCH] D94579: [RISCV] add the MC layer support of P extension

[Jim Lin via Phabricator via llvm-commits]

Jim added inline comments.


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Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoP.td:115
+def ADD16    : ALU_P_rr<0b0100000, 0b000, "add16">;
+def ADD64    : ALU_P_rr<0b1100000, 0b001, "add64">;
+def AVE      : ALU_P_rr<0b1110000, 0b000, "ave">;
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In RV32, ADD64's input operand is even/odd pair of registers.


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  https://reviews.llvm.org/D94579/new/

https://reviews.llvm.org/D94579