[llvm] 3aeb30d - [ARM] Additional tests for different interleaving patterns. NFC
David Green via llvm-commits
llvm-commits at lists.llvm.org
Wed Jan 13 00:32:06 PST 2021
Author: David Green
Date: 2021-01-13T08:31:50Z
New Revision: 3aeb30d1a68a76616c699587e07a7d8880c29d1c
URL: https://github.com/llvm/llvm-project/commit/3aeb30d1a68a76616c699587e07a7d8880c29d1c
DIFF: https://github.com/llvm/llvm-project/commit/3aeb30d1a68a76616c699587e07a7d8880c29d1c.diff
LOG: [ARM] Additional tests for different interleaving patterns. NFC
Added:
Modified:
llvm/test/CodeGen/Thumb2/mve-shuffleext.ll
llvm/test/CodeGen/Thumb2/mve-vcvt.ll
llvm/test/CodeGen/Thumb2/mve-vmovnstore.ll
llvm/test/CodeGen/Thumb2/mve-vqdmulh.ll
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/Thumb2/mve-shuffleext.ll b/llvm/test/CodeGen/Thumb2/mve-shuffleext.ll
index c7165e71b5dd..715be1d921ca 100644
--- a/llvm/test/CodeGen/Thumb2/mve-shuffleext.ll
+++ b/llvm/test/CodeGen/Thumb2/mve-shuffleext.ll
@@ -14,6 +14,33 @@ entry:
ret <4 x i32> %out
}
+define arm_aapcs_vfpcc <4 x i32> @sext_i32_0246_swapped(<8 x i16> %src) {
+; CHECK-LABEL: sext_i32_0246_swapped:
+; CHECK: @ %bb.0: @ %entry
+; CHECK-NEXT: vmov.u16 r0, q0[2]
+; CHECK-NEXT: vmov.u16 r1, q0[0]
+; CHECK-NEXT: vmov q1[2], q1[0], r1, r0
+; CHECK-NEXT: vmov.u16 r0, q0[3]
+; CHECK-NEXT: vmov.u16 r1, q0[1]
+; CHECK-NEXT: vmov q1[3], q1[1], r1, r0
+; CHECK-NEXT: vmov.u16 r0, q0[6]
+; CHECK-NEXT: vmov.u16 r1, q0[4]
+; CHECK-NEXT: vmov q2[2], q2[0], r1, r0
+; CHECK-NEXT: vmov.u16 r0, q0[7]
+; CHECK-NEXT: vmov.u16 r1, q0[5]
+; CHECK-NEXT: vmovlb.s16 q0, q1
+; CHECK-NEXT: vmov q2[3], q2[1], r1, r0
+; CHECK-NEXT: vmov.f32 s1, s2
+; CHECK-NEXT: vmovlb.s16 q2, q2
+; CHECK-NEXT: vmov.f32 s2, s8
+; CHECK-NEXT: vmov.f32 s3, s10
+; CHECK-NEXT: bx lr
+entry:
+ %out = sext <8 x i16> %src to <8 x i32>
+ %strided.vec = shufflevector <8 x i32> %out, <8 x i32> undef, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
+ ret <4 x i32> %strided.vec
+}
+
define arm_aapcs_vfpcc <4 x i32> @sext_i32_1357(<8 x i16> %src) {
; CHECK-LABEL: sext_i32_1357:
; CHECK: @ %bb.0: @ %entry
@@ -25,6 +52,34 @@ entry:
ret <4 x i32> %out
}
+define arm_aapcs_vfpcc <4 x i32> @sext_i32_1357_swapped(<8 x i16> %src) {
+; CHECK-LABEL: sext_i32_1357_swapped:
+; CHECK: @ %bb.0: @ %entry
+; CHECK-NEXT: vmov.u16 r0, q0[2]
+; CHECK-NEXT: vmov.u16 r1, q0[0]
+; CHECK-NEXT: vmov q1[2], q1[0], r1, r0
+; CHECK-NEXT: vmov.u16 r0, q0[3]
+; CHECK-NEXT: vmov.u16 r1, q0[1]
+; CHECK-NEXT: vmov q1[3], q1[1], r1, r0
+; CHECK-NEXT: vmov.u16 r0, q0[6]
+; CHECK-NEXT: vmov.u16 r1, q0[4]
+; CHECK-NEXT: vmovlb.s16 q1, q1
+; CHECK-NEXT: vmov q2[2], q2[0], r1, r0
+; CHECK-NEXT: vmov.u16 r0, q0[7]
+; CHECK-NEXT: vmov.u16 r1, q0[5]
+; CHECK-NEXT: vmov.f32 s0, s5
+; CHECK-NEXT: vmov q2[3], q2[1], r1, r0
+; CHECK-NEXT: vmov.f32 s1, s7
+; CHECK-NEXT: vmovlb.s16 q2, q2
+; CHECK-NEXT: vmov.f32 s2, s9
+; CHECK-NEXT: vmov.f32 s3, s11
+; CHECK-NEXT: bx lr
+entry:
+ %out = sext <8 x i16> %src to <8 x i32>
+ %strided.vec = shufflevector <8 x i32> %out, <8 x i32> undef, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
+ ret <4 x i32> %strided.vec
+}
+
define arm_aapcs_vfpcc <8 x i32> @sext_i32_02468101214(<16 x i16> %src) {
; CHECK-LABEL: sext_i32_02468101214:
; CHECK: @ %bb.0: @ %entry
@@ -37,6 +92,50 @@ entry:
ret <8 x i32> %out
}
+define arm_aapcs_vfpcc <8 x i32> @sext_i32_02468101214_swapped(<16 x i16> %src) {
+; CHECK-LABEL: sext_i32_02468101214_swapped:
+; CHECK: @ %bb.0: @ %entry
+; CHECK-NEXT: vmov.u16 r0, q0[2]
+; CHECK-NEXT: vmov.u16 r1, q0[0]
+; CHECK-NEXT: vmov q2[2], q2[0], r1, r0
+; CHECK-NEXT: vmov.u16 r0, q0[3]
+; CHECK-NEXT: vmov.u16 r1, q0[1]
+; CHECK-NEXT: vmov q2[3], q2[1], r1, r0
+; CHECK-NEXT: vmov.u16 r0, q0[6]
+; CHECK-NEXT: vmov.u16 r1, q0[4]
+; CHECK-NEXT: vmov q3[2], q3[0], r1, r0
+; CHECK-NEXT: vmov.u16 r0, q0[7]
+; CHECK-NEXT: vmov.u16 r1, q0[5]
+; CHECK-NEXT: vmovlb.s16 q0, q2
+; CHECK-NEXT: vmov q3[3], q3[1], r1, r0
+; CHECK-NEXT: vmov.u16 r0, q1[2]
+; CHECK-NEXT: vmov.u16 r1, q1[0]
+; CHECK-NEXT: vmovlb.s16 q3, q3
+; CHECK-NEXT: vmov.f32 s1, s2
+; CHECK-NEXT: vmov q2[2], q2[0], r1, r0
+; CHECK-NEXT: vmov.u16 r0, q1[3]
+; CHECK-NEXT: vmov.u16 r1, q1[1]
+; CHECK-NEXT: vmov.f32 s2, s12
+; CHECK-NEXT: vmov q2[3], q2[1], r1, r0
+; CHECK-NEXT: vmov.u16 r0, q1[6]
+; CHECK-NEXT: vmov.u16 r1, q1[4]
+; CHECK-NEXT: vmov.f32 s3, s14
+; CHECK-NEXT: vmov q3[2], q3[0], r1, r0
+; CHECK-NEXT: vmov.u16 r0, q1[7]
+; CHECK-NEXT: vmov.u16 r1, q1[5]
+; CHECK-NEXT: vmovlb.s16 q1, q2
+; CHECK-NEXT: vmov q3[3], q3[1], r1, r0
+; CHECK-NEXT: vmovlb.s16 q3, q3
+; CHECK-NEXT: vmov.f32 s5, s6
+; CHECK-NEXT: vmov.f32 s6, s12
+; CHECK-NEXT: vmov.f32 s7, s14
+; CHECK-NEXT: bx lr
+entry:
+ %out = sext <16 x i16> %src to <16 x i32>
+ %strided.vec = shufflevector <16 x i32> %out, <16 x i32> undef, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>
+ ret <8 x i32> %strided.vec
+}
+
define arm_aapcs_vfpcc <8 x i32> @sext_i32_13579111315(<16 x i16> %src) {
; CHECK-LABEL: sext_i32_13579111315:
; CHECK: @ %bb.0: @ %entry
@@ -49,6 +148,52 @@ entry:
ret <8 x i32> %out
}
+define arm_aapcs_vfpcc <8 x i32> @sext_i32_13579111315_swapped(<16 x i16> %src) {
+; CHECK-LABEL: sext_i32_13579111315_swapped:
+; CHECK: @ %bb.0: @ %entry
+; CHECK-NEXT: vmov.u16 r0, q0[2]
+; CHECK-NEXT: vmov.u16 r1, q0[0]
+; CHECK-NEXT: vmov q2[2], q2[0], r1, r0
+; CHECK-NEXT: vmov.u16 r0, q0[3]
+; CHECK-NEXT: vmov.u16 r1, q0[1]
+; CHECK-NEXT: vmov q2[3], q2[1], r1, r0
+; CHECK-NEXT: vmov.u16 r0, q0[6]
+; CHECK-NEXT: vmov.u16 r1, q0[4]
+; CHECK-NEXT: vmovlb.s16 q2, q2
+; CHECK-NEXT: vmov q3[2], q3[0], r1, r0
+; CHECK-NEXT: vmov.u16 r0, q0[7]
+; CHECK-NEXT: vmov.u16 r1, q0[5]
+; CHECK-NEXT: vmov.f32 s0, s9
+; CHECK-NEXT: vmov q3[3], q3[1], r1, r0
+; CHECK-NEXT: vmov.u16 r0, q1[2]
+; CHECK-NEXT: vmov.u16 r1, q1[0]
+; CHECK-NEXT: vmov.f32 s1, s11
+; CHECK-NEXT: vmov q2[2], q2[0], r1, r0
+; CHECK-NEXT: vmovlb.s16 q3, q3
+; CHECK-NEXT: vmov.u16 r0, q1[3]
+; CHECK-NEXT: vmov.u16 r1, q1[1]
+; CHECK-NEXT: vmov q2[3], q2[1], r1, r0
+; CHECK-NEXT: vmov.f32 s2, s13
+; CHECK-NEXT: vmov.u16 r0, q1[6]
+; CHECK-NEXT: vmov.u16 r1, q1[4]
+; CHECK-NEXT: vmov.f32 s3, s15
+; CHECK-NEXT: vmov q3[2], q3[0], r1, r0
+; CHECK-NEXT: vmov.u16 r0, q1[7]
+; CHECK-NEXT: vmov.u16 r1, q1[5]
+; CHECK-NEXT: vmovlb.s16 q2, q2
+; CHECK-NEXT: vmov q3[3], q3[1], r1, r0
+; CHECK-NEXT: vmov.f32 s4, s9
+; CHECK-NEXT: vmovlb.s16 q3, q3
+; CHECK-NEXT: vmov.f32 s5, s11
+; CHECK-NEXT: vmov.f32 s6, s13
+; CHECK-NEXT: vmov.f32 s7, s15
+; CHECK-NEXT: bx lr
+entry:
+ %out = sext <16 x i16> %src to <16 x i32>
+ %strided.vec = shufflevector <16 x i32> %out, <16 x i32> undef, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>
+ ret <8 x i32> %strided.vec
+}
+
define arm_aapcs_vfpcc <4 x i32> @zext_i32_0246(<8 x i16> %src) {
; CHECK-LABEL: zext_i32_0246:
; CHECK: @ %bb.0: @ %entry
@@ -60,6 +205,27 @@ entry:
ret <4 x i32> %out
}
+define arm_aapcs_vfpcc <4 x i32> @zext_i32_0246_swapped(<8 x i16> %src) {
+; CHECK-LABEL: zext_i32_0246_swapped:
+; CHECK: @ %bb.0: @ %entry
+; CHECK-NEXT: vmov.u16 r0, q0[2]
+; CHECK-NEXT: vmov.u16 r1, q0[0]
+; CHECK-NEXT: vmov q1[2], q1[0], r1, r0
+; CHECK-NEXT: vmov.u16 r0, q0[6]
+; CHECK-NEXT: vmov.u16 r1, q0[4]
+; CHECK-NEXT: vmov q0[2], q0[0], r1, r0
+; CHECK-NEXT: vmovlb.u16 q2, q0
+; CHECK-NEXT: vmovlb.u16 q0, q1
+; CHECK-NEXT: vmov.f32 s1, s2
+; CHECK-NEXT: vmov.f32 s2, s8
+; CHECK-NEXT: vmov.f32 s3, s10
+; CHECK-NEXT: bx lr
+entry:
+ %out = zext <8 x i16> %src to <8 x i32>
+ %strided.vec = shufflevector <8 x i32> %out, <8 x i32> undef, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
+ ret <4 x i32> %strided.vec
+}
+
define arm_aapcs_vfpcc <4 x i32> @zext_i32_1357(<8 x i16> %src) {
; CHECK-LABEL: zext_i32_1357:
; CHECK: @ %bb.0: @ %entry
@@ -71,6 +237,28 @@ entry:
ret <4 x i32> %out
}
+define arm_aapcs_vfpcc <4 x i32> @zext_i32_1357_swapped(<8 x i16> %src) {
+; CHECK-LABEL: zext_i32_1357_swapped:
+; CHECK: @ %bb.0: @ %entry
+; CHECK-NEXT: vmov.u16 r0, q0[3]
+; CHECK-NEXT: vmov.u16 r1, q0[1]
+; CHECK-NEXT: vmov q1[3], q1[1], r1, r0
+; CHECK-NEXT: vmov.u16 r0, q0[7]
+; CHECK-NEXT: vmov.u16 r1, q0[5]
+; CHECK-NEXT: vmovlb.u16 q1, q1
+; CHECK-NEXT: vmov q0[3], q0[1], r1, r0
+; CHECK-NEXT: vmovlb.u16 q2, q0
+; CHECK-NEXT: vmov.f32 s0, s5
+; CHECK-NEXT: vmov.f32 s1, s7
+; CHECK-NEXT: vmov.f32 s2, s9
+; CHECK-NEXT: vmov.f32 s3, s11
+; CHECK-NEXT: bx lr
+entry:
+ %out = zext <8 x i16> %src to <8 x i32>
+ %strided.vec = shufflevector <8 x i32> %out, <8 x i32> undef, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
+ ret <4 x i32> %strided.vec
+}
+
define arm_aapcs_vfpcc <8 x i32> @zext_i32_02468101214(<16 x i16> %src) {
; CHECK-LABEL: zext_i32_02468101214:
; CHECK: @ %bb.0: @ %entry
@@ -83,6 +271,38 @@ entry:
ret <8 x i32> %out
}
+define arm_aapcs_vfpcc <8 x i32> @zext_i32_02468101214_swapped(<16 x i16> %src) {
+; CHECK-LABEL: zext_i32_02468101214_swapped:
+; CHECK: @ %bb.0: @ %entry
+; CHECK-NEXT: vmov.u16 r0, q0[2]
+; CHECK-NEXT: vmov.u16 r1, q0[0]
+; CHECK-NEXT: vmov q2[2], q2[0], r1, r0
+; CHECK-NEXT: vmov.u16 r0, q0[6]
+; CHECK-NEXT: vmov.u16 r1, q0[4]
+; CHECK-NEXT: vmov q0[2], q0[0], r1, r0
+; CHECK-NEXT: vmov.u16 r0, q1[2]
+; CHECK-NEXT: vmovlb.u16 q3, q0
+; CHECK-NEXT: vmovlb.u16 q0, q2
+; CHECK-NEXT: vmov.u16 r1, q1[0]
+; CHECK-NEXT: vmov.f32 s1, s2
+; CHECK-NEXT: vmov q2[2], q2[0], r1, r0
+; CHECK-NEXT: vmov.u16 r0, q1[6]
+; CHECK-NEXT: vmov.u16 r1, q1[4]
+; CHECK-NEXT: vmov.f32 s2, s12
+; CHECK-NEXT: vmov q1[2], q1[0], r1, r0
+; CHECK-NEXT: vmov.f32 s3, s14
+; CHECK-NEXT: vmovlb.u16 q3, q1
+; CHECK-NEXT: vmovlb.u16 q1, q2
+; CHECK-NEXT: vmov.f32 s5, s6
+; CHECK-NEXT: vmov.f32 s6, s12
+; CHECK-NEXT: vmov.f32 s7, s14
+; CHECK-NEXT: bx lr
+entry:
+ %out = zext <16 x i16> %src to <16 x i32>
+ %strided.vec = shufflevector <16 x i32> %out, <16 x i32> undef, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>
+ ret <8 x i32> %strided.vec
+}
+
define arm_aapcs_vfpcc <8 x i32> @zext_i32_13579111315(<16 x i16> %src) {
; CHECK-LABEL: zext_i32_13579111315:
; CHECK: @ %bb.0: @ %entry
@@ -95,6 +315,53 @@ entry:
ret <8 x i32> %out
}
+define arm_aapcs_vfpcc <8 x i32> @zext_i32_13579111315_swapped(<16 x i16> %src) {
+; CHECK-LABEL: zext_i32_13579111315_swapped:
+; CHECK: @ %bb.0: @ %entry
+; CHECK-NEXT: vmov.u16 r0, q0[3]
+; CHECK-NEXT: vmov.u16 r1, q0[1]
+; CHECK-NEXT: vmov q2[3], q2[1], r1, r0
+; CHECK-NEXT: vmov.u16 r0, q0[7]
+; CHECK-NEXT: vmov.u16 r1, q0[5]
+; CHECK-NEXT: vmovlb.u16 q2, q2
+; CHECK-NEXT: vmov q0[3], q0[1], r1, r0
+; CHECK-NEXT: vmov.u16 r0, q1[3]
+; CHECK-NEXT: vmovlb.u16 q3, q0
+; CHECK-NEXT: vmov.f32 s0, s9
+; CHECK-NEXT: vmov.u16 r1, q1[1]
+; CHECK-NEXT: vmov.f32 s1, s11
+; CHECK-NEXT: vmov q2[3], q2[1], r1, r0
+; CHECK-NEXT: vmov.u16 r0, q1[7]
+; CHECK-NEXT: vmov.u16 r1, q1[5]
+; CHECK-NEXT: vmov.f32 s2, s13
+; CHECK-NEXT: vmov q1[3], q1[1], r1, r0
+; CHECK-NEXT: vmovlb.u16 q2, q2
+; CHECK-NEXT: vmov.f32 s3, s15
+; CHECK-NEXT: vmovlb.u16 q3, q1
+; CHECK-NEXT: vmov.f32 s4, s9
+; CHECK-NEXT: vmov.f32 s5, s11
+; CHECK-NEXT: vmov.f32 s6, s13
+; CHECK-NEXT: vmov.f32 s7, s15
+; CHECK-NEXT: bx lr
+entry:
+ %out = zext <16 x i16> %src to <16 x i32>
+ %strided.vec = shufflevector <16 x i32> %out, <16 x i32> undef, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>
+ ret <8 x i32> %strided.vec
+}
+
+define arm_aapcs_vfpcc <8 x i32> @sext_i32_02481357(<8 x i16> %src) {
+; CHECK-LABEL: sext_i32_02481357:
+; CHECK: @ %bb.0: @ %entry
+; CHECK-NEXT: vmovlb.s16 q2, q0
+; CHECK-NEXT: vmovlt.s16 q1, q0
+; CHECK-NEXT: vmov q0, q2
+; CHECK-NEXT: bx lr
+entry:
+ %strided.vec = shufflevector <8 x i16> %src, <8 x i16> undef, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 1, i32 3, i32 5, i32 7>
+ %out = sext <8 x i16> %strided.vec to <8 x i32>
+ ret <8 x i32> %out
+}
+
; i8 -> i16
diff --git a/llvm/test/CodeGen/Thumb2/mve-vcvt.ll b/llvm/test/CodeGen/Thumb2/mve-vcvt.ll
index 2b165881badf..851be7124e5b 100644
--- a/llvm/test/CodeGen/Thumb2/mve-vcvt.ll
+++ b/llvm/test/CodeGen/Thumb2/mve-vcvt.ll
@@ -387,3 +387,54 @@ entry:
%out = fptoui <2 x double> %src to <2 x i64>
ret <2 x i64> %out
}
+
+define arm_aapcs_vfpcc <8 x half> @vmovn32_trunc1(<4 x float> %src1, <4 x float> %src2) {
+; CHECK-MVE-LABEL: vmovn32_trunc1:
+; CHECK-MVE: @ %bb.0: @ %entry
+; CHECK-MVE-NEXT: vmov q2, q0
+; CHECK-MVE-NEXT: vcvtb.f16.f32 s0, s8
+; CHECK-MVE-NEXT: vcvtt.f16.f32 s0, s4
+; CHECK-MVE-NEXT: vcvtb.f16.f32 s1, s9
+; CHECK-MVE-NEXT: vcvtt.f16.f32 s1, s5
+; CHECK-MVE-NEXT: vcvtb.f16.f32 s2, s10
+; CHECK-MVE-NEXT: vcvtt.f16.f32 s2, s6
+; CHECK-MVE-NEXT: vcvtb.f16.f32 s3, s11
+; CHECK-MVE-NEXT: vcvtt.f16.f32 s3, s7
+; CHECK-MVE-NEXT: bx lr
+;
+; CHECK-MVEFP-LABEL: vmovn32_trunc1:
+; CHECK-MVEFP: @ %bb.0: @ %entry
+; CHECK-MVEFP-NEXT: vcvtb.f16.f32 q0, q0
+; CHECK-MVEFP-NEXT: vcvtt.f16.f32 q0, q1
+; CHECK-MVEFP-NEXT: bx lr
+entry:
+ %strided.vec = shufflevector <4 x float> %src1, <4 x float> %src2, <8 x i32> <i32 0, i32 4, i32 1, i32 5, i32 2, i32 6, i32 3, i32 7>
+ %out = fptrunc <8 x float> %strided.vec to <8 x half>
+ ret <8 x half> %out
+}
+
+define arm_aapcs_vfpcc <8 x half> @vmovn32_trunc2(<4 x float> %src1, <4 x float> %src2) {
+; CHECK-MVE-LABEL: vmovn32_trunc2:
+; CHECK-MVE: @ %bb.0: @ %entry
+; CHECK-MVE-NEXT: vmov q2, q0
+; CHECK-MVE-NEXT: vcvtb.f16.f32 s0, s4
+; CHECK-MVE-NEXT: vcvtt.f16.f32 s0, s8
+; CHECK-MVE-NEXT: vcvtb.f16.f32 s1, s5
+; CHECK-MVE-NEXT: vcvtt.f16.f32 s1, s9
+; CHECK-MVE-NEXT: vcvtb.f16.f32 s2, s6
+; CHECK-MVE-NEXT: vcvtt.f16.f32 s2, s10
+; CHECK-MVE-NEXT: vcvtb.f16.f32 s3, s7
+; CHECK-MVE-NEXT: vcvtt.f16.f32 s3, s11
+; CHECK-MVE-NEXT: bx lr
+;
+; CHECK-MVEFP-LABEL: vmovn32_trunc2:
+; CHECK-MVEFP: @ %bb.0: @ %entry
+; CHECK-MVEFP-NEXT: vcvtb.f16.f32 q1, q1
+; CHECK-MVEFP-NEXT: vcvtt.f16.f32 q1, q0
+; CHECK-MVEFP-NEXT: vmov q0, q1
+; CHECK-MVEFP-NEXT: bx lr
+entry:
+ %strided.vec = shufflevector <4 x float> %src1, <4 x float> %src2, <8 x i32> <i32 4, i32 0, i32 5, i32 1, i32 6, i32 2, i32 7, i32 3>
+ %out = fptrunc <8 x float> %strided.vec to <8 x half>
+ ret <8 x half> %out
+}
diff --git a/llvm/test/CodeGen/Thumb2/mve-vmovnstore.ll b/llvm/test/CodeGen/Thumb2/mve-vmovnstore.ll
index b9856298defc..f9a535e9d2dc 100644
--- a/llvm/test/CodeGen/Thumb2/mve-vmovnstore.ll
+++ b/llvm/test/CodeGen/Thumb2/mve-vmovnstore.ll
@@ -27,6 +27,48 @@ entry:
ret void
}
+define arm_aapcs_vfpcc void @vmovn32_trunc1_onesrc(<8 x i32> %src1, <8 x i16> *%dest) {
+; CHECK-LABEL: vmovn32_trunc1_onesrc:
+; CHECK: @ %bb.0: @ %entry
+; CHECK-NEXT: vmov.f32 s8, s2
+; CHECK-NEXT: vmov.f32 s9, s6
+; CHECK-NEXT: vmov.f32 s10, s3
+; CHECK-NEXT: vmov.f32 s11, s7
+; CHECK-NEXT: vstrh.32 q2, [r0, #8]
+; CHECK-NEXT: vmov.f32 s8, s0
+; CHECK-NEXT: vmov.f32 s9, s4
+; CHECK-NEXT: vmov.f32 s10, s1
+; CHECK-NEXT: vmov.f32 s11, s5
+; CHECK-NEXT: vstrh.32 q2, [r0]
+; CHECK-NEXT: bx lr
+entry:
+ %strided.vec = shufflevector <8 x i32> %src1, <8 x i32> undef, <8 x i32> <i32 0, i32 4, i32 1, i32 5, i32 2, i32 6, i32 3, i32 7>
+ %out = trunc <8 x i32> %strided.vec to <8 x i16>
+ store <8 x i16> %out, <8 x i16> *%dest, align 8
+ ret void
+}
+
+define arm_aapcs_vfpcc void @vmovn32_trunc2_onesrc(<8 x i32> %src1, <8 x i16> *%dest) {
+; CHECK-LABEL: vmovn32_trunc2_onesrc:
+; CHECK: @ %bb.0: @ %entry
+; CHECK-NEXT: vmov.f32 s8, s6
+; CHECK-NEXT: vmov.f32 s9, s2
+; CHECK-NEXT: vmov.f32 s10, s7
+; CHECK-NEXT: vmov.f32 s11, s3
+; CHECK-NEXT: vstrh.32 q2, [r0, #8]
+; CHECK-NEXT: vmov.f32 s8, s4
+; CHECK-NEXT: vmov.f32 s9, s0
+; CHECK-NEXT: vmov.f32 s10, s5
+; CHECK-NEXT: vmov.f32 s11, s1
+; CHECK-NEXT: vstrh.32 q2, [r0]
+; CHECK-NEXT: bx lr
+entry:
+ %strided.vec = shufflevector <8 x i32> %src1, <8 x i32> undef, <8 x i32> <i32 4, i32 0, i32 5, i32 1, i32 6, i32 2, i32 7, i32 3>
+ %out = trunc <8 x i32> %strided.vec to <8 x i16>
+ store <8 x i16> %out, <8 x i16> *%dest, align 8
+ ret void
+}
+
define arm_aapcs_vfpcc void @vmovn16_trunc1(<8 x i16> %src1, <8 x i16> %src2, <16 x i8> *%dest) {
; CHECK-LABEL: vmovn16_trunc1:
; CHECK: @ %bb.0: @ %entry
@@ -53,6 +95,96 @@ entry:
ret void
}
+define arm_aapcs_vfpcc void @vmovn16_trunc1_onesrc(<16 x i16> %src1, <16 x i8> *%dest) {
+; CHECK-LABEL: vmovn16_trunc1_onesrc:
+; CHECK: @ %bb.0: @ %entry
+; CHECK-NEXT: vmov.u16 r1, q0[4]
+; CHECK-NEXT: vmov.16 q2[0], r1
+; CHECK-NEXT: vmov.u16 r1, q1[4]
+; CHECK-NEXT: vmov.16 q2[1], r1
+; CHECK-NEXT: vmov.u16 r1, q0[5]
+; CHECK-NEXT: vmov.16 q2[2], r1
+; CHECK-NEXT: vmov.u16 r1, q1[5]
+; CHECK-NEXT: vmov.16 q2[3], r1
+; CHECK-NEXT: vmov.u16 r1, q0[6]
+; CHECK-NEXT: vmov.16 q2[4], r1
+; CHECK-NEXT: vmov.u16 r1, q1[6]
+; CHECK-NEXT: vmov.16 q2[5], r1
+; CHECK-NEXT: vmov.u16 r1, q0[7]
+; CHECK-NEXT: vmov.16 q2[6], r1
+; CHECK-NEXT: vmov.u16 r1, q1[7]
+; CHECK-NEXT: vmov.16 q2[7], r1
+; CHECK-NEXT: vmov.u16 r1, q0[0]
+; CHECK-NEXT: vstrb.16 q2, [r0, #8]
+; CHECK-NEXT: vmov.16 q2[0], r1
+; CHECK-NEXT: vmov.u16 r1, q1[0]
+; CHECK-NEXT: vmov.16 q2[1], r1
+; CHECK-NEXT: vmov.u16 r1, q0[1]
+; CHECK-NEXT: vmov.16 q2[2], r1
+; CHECK-NEXT: vmov.u16 r1, q1[1]
+; CHECK-NEXT: vmov.16 q2[3], r1
+; CHECK-NEXT: vmov.u16 r1, q0[2]
+; CHECK-NEXT: vmov.16 q2[4], r1
+; CHECK-NEXT: vmov.u16 r1, q1[2]
+; CHECK-NEXT: vmov.16 q2[5], r1
+; CHECK-NEXT: vmov.u16 r1, q0[3]
+; CHECK-NEXT: vmov.16 q2[6], r1
+; CHECK-NEXT: vmov.u16 r1, q1[3]
+; CHECK-NEXT: vmov.16 q2[7], r1
+; CHECK-NEXT: vstrb.16 q2, [r0]
+; CHECK-NEXT: bx lr
+entry:
+ %strided.vec = shufflevector <16 x i16> %src1, <16 x i16> undef, <16 x i32> <i32 0, i32 8, i32 1, i32 9, i32 2, i32 10, i32 3, i32 11, i32 4, i32 12, i32 5, i32 13, i32 6, i32 14, i32 7, i32 15>
+ %out = trunc <16 x i16> %strided.vec to <16 x i8>
+ store <16 x i8> %out, <16 x i8> *%dest, align 8
+ ret void
+}
+
+define arm_aapcs_vfpcc void @vmovn16_trunc2_onesrc(<16 x i16> %src1, <16 x i8> *%dest) {
+; CHECK-LABEL: vmovn16_trunc2_onesrc:
+; CHECK: @ %bb.0: @ %entry
+; CHECK-NEXT: vmov.u16 r1, q1[4]
+; CHECK-NEXT: vmov.16 q2[0], r1
+; CHECK-NEXT: vmov.u16 r1, q0[4]
+; CHECK-NEXT: vmov.16 q2[1], r1
+; CHECK-NEXT: vmov.u16 r1, q1[5]
+; CHECK-NEXT: vmov.16 q2[2], r1
+; CHECK-NEXT: vmov.u16 r1, q0[5]
+; CHECK-NEXT: vmov.16 q2[3], r1
+; CHECK-NEXT: vmov.u16 r1, q1[6]
+; CHECK-NEXT: vmov.16 q2[4], r1
+; CHECK-NEXT: vmov.u16 r1, q0[6]
+; CHECK-NEXT: vmov.16 q2[5], r1
+; CHECK-NEXT: vmov.u16 r1, q1[7]
+; CHECK-NEXT: vmov.16 q2[6], r1
+; CHECK-NEXT: vmov.u16 r1, q0[7]
+; CHECK-NEXT: vmov.16 q2[7], r1
+; CHECK-NEXT: vmov.u16 r1, q1[0]
+; CHECK-NEXT: vstrb.16 q2, [r0, #8]
+; CHECK-NEXT: vmov.16 q2[0], r1
+; CHECK-NEXT: vmov.u16 r1, q0[0]
+; CHECK-NEXT: vmov.16 q2[1], r1
+; CHECK-NEXT: vmov.u16 r1, q1[1]
+; CHECK-NEXT: vmov.16 q2[2], r1
+; CHECK-NEXT: vmov.u16 r1, q0[1]
+; CHECK-NEXT: vmov.16 q2[3], r1
+; CHECK-NEXT: vmov.u16 r1, q1[2]
+; CHECK-NEXT: vmov.16 q2[4], r1
+; CHECK-NEXT: vmov.u16 r1, q0[2]
+; CHECK-NEXT: vmov.16 q2[5], r1
+; CHECK-NEXT: vmov.u16 r1, q1[3]
+; CHECK-NEXT: vmov.16 q2[6], r1
+; CHECK-NEXT: vmov.u16 r1, q0[3]
+; CHECK-NEXT: vmov.16 q2[7], r1
+; CHECK-NEXT: vstrb.16 q2, [r0]
+; CHECK-NEXT: bx lr
+entry:
+ %strided.vec = shufflevector <16 x i16> %src1, <16 x i16> undef, <16 x i32> <i32 8, i32 0, i32 9, i32 1, i32 10, i32 2, i32 11, i32 3, i32 12, i32 4, i32 13, i32 5, i32 14, i32 6, i32 15, i32 7>
+ %out = trunc <16 x i16> %strided.vec to <16 x i8>
+ store <16 x i8> %out, <16 x i8> *%dest, align 8
+ ret void
+}
+
define arm_aapcs_vfpcc void @vmovn64_t1(<2 x i64> %src1, <2 x i64> %src2, <2 x i64> *%dest) {
; CHECK-LABEL: vmovn64_t1:
diff --git a/llvm/test/CodeGen/Thumb2/mve-vqdmulh.ll b/llvm/test/CodeGen/Thumb2/mve-vqdmulh.ll
index e8979b439a0b..6722aa706769 100644
--- a/llvm/test/CodeGen/Thumb2/mve-vqdmulh.ll
+++ b/llvm/test/CodeGen/Thumb2/mve-vqdmulh.ll
@@ -137,6 +137,75 @@ entry:
ret <8 x i16> %l10
}
+define arm_aapcs_vfpcc <8 x i16> @vqdmulh_i16_interleaved(<8 x i16> %s0, <8 x i16> %s1) {
+; CHECK-LABEL: vqdmulh_i16_interleaved:
+; CHECK: @ %bb.0: @ %entry
+; CHECK-NEXT: vmov.u16 r0, q0[0]
+; CHECK-NEXT: vmov.16 q2[0], r0
+; CHECK-NEXT: vmov.u16 r0, q0[2]
+; CHECK-NEXT: vmov.16 q2[1], r0
+; CHECK-NEXT: vmov.u16 r0, q0[4]
+; CHECK-NEXT: vmov.16 q2[2], r0
+; CHECK-NEXT: vmov.u16 r0, q0[6]
+; CHECK-NEXT: vmov.16 q2[3], r0
+; CHECK-NEXT: vmov.u16 r0, q0[1]
+; CHECK-NEXT: vmov.16 q2[4], r0
+; CHECK-NEXT: vmov.u16 r0, q0[3]
+; CHECK-NEXT: vmov.16 q2[5], r0
+; CHECK-NEXT: vmov.u16 r0, q0[5]
+; CHECK-NEXT: vmov.16 q2[6], r0
+; CHECK-NEXT: vmov.u16 r0, q0[7]
+; CHECK-NEXT: vmov.16 q2[7], r0
+; CHECK-NEXT: vmov.u16 r0, q1[0]
+; CHECK-NEXT: vmov.16 q0[0], r0
+; CHECK-NEXT: vmov.u16 r0, q1[2]
+; CHECK-NEXT: vmov.16 q0[1], r0
+; CHECK-NEXT: vmov.u16 r0, q1[4]
+; CHECK-NEXT: vmov.16 q0[2], r0
+; CHECK-NEXT: vmov.u16 r0, q1[6]
+; CHECK-NEXT: vmov.16 q0[3], r0
+; CHECK-NEXT: vmov.u16 r0, q1[1]
+; CHECK-NEXT: vmov.16 q0[4], r0
+; CHECK-NEXT: vmov.u16 r0, q1[3]
+; CHECK-NEXT: vmov.16 q0[5], r0
+; CHECK-NEXT: vmov.u16 r0, q1[5]
+; CHECK-NEXT: vmov.16 q0[6], r0
+; CHECK-NEXT: vmov.u16 r0, q1[7]
+; CHECK-NEXT: vmov.16 q0[7], r0
+; CHECK-NEXT: vqdmulh.s16 q1, q0, q2
+; CHECK-NEXT: vmov.u16 r0, q1[0]
+; CHECK-NEXT: vmov.16 q0[0], r0
+; CHECK-NEXT: vmov.u16 r0, q1[4]
+; CHECK-NEXT: vmov.16 q0[1], r0
+; CHECK-NEXT: vmov.u16 r0, q1[1]
+; CHECK-NEXT: vmov.16 q0[2], r0
+; CHECK-NEXT: vmov.u16 r0, q1[5]
+; CHECK-NEXT: vmov.16 q0[3], r0
+; CHECK-NEXT: vmov.u16 r0, q1[2]
+; CHECK-NEXT: vmov.16 q0[4], r0
+; CHECK-NEXT: vmov.u16 r0, q1[6]
+; CHECK-NEXT: vmov.16 q0[5], r0
+; CHECK-NEXT: vmov.u16 r0, q1[3]
+; CHECK-NEXT: vmov.16 q0[6], r0
+; CHECK-NEXT: vmov.u16 r0, q1[7]
+; CHECK-NEXT: vmov.16 q0[7], r0
+; CHECK-NEXT: bx lr
+entry:
+ %0 = shufflevector <8 x i16> %s0, <8 x i16> undef, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 1, i32 3, i32 5, i32 7>
+ %1 = sext <8 x i16> %0 to <8 x i32>
+ %l2 = sext <8 x i16> %s0 to <8 x i32>
+ %2 = shufflevector <8 x i16> %s1, <8 x i16> undef, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 1, i32 3, i32 5, i32 7>
+ %3 = sext <8 x i16> %2 to <8 x i32>
+ %l5 = sext <8 x i16> %s1 to <8 x i32>
+ %l6 = mul nsw <8 x i32> %3, %1
+ %l7 = ashr <8 x i32> %l6, <i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15>
+ %l8 = icmp slt <8 x i32> %l7, <i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767>
+ %l9 = select <8 x i1> %l8, <8 x i32> %l7, <8 x i32> <i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767>
+ %l10 = trunc <8 x i32> %l9 to <8 x i16>
+ %4 = shufflevector <8 x i16> %l10, <8 x i16> undef, <8 x i32> <i32 0, i32 4, i32 1, i32 5, i32 2, i32 6, i32 3, i32 7>
+ ret <8 x i16> %4
+}
+
define arm_aapcs_vfpcc i64 @vqdmulh_i32(<4 x i32> %s0, <4 x i32> %s1) {
; CHECK-LABEL: vqdmulh_i32:
; CHECK: @ %bb.0: @ %entry
@@ -180,13 +249,13 @@ define void @vqdmulh_loop_i8(i8* nocapture readonly %x, i8* nocapture readonly %
; CHECK-NEXT: push {r7, lr}
; CHECK-NEXT: mov.w lr, #64
; CHECK-NEXT: dls lr, lr
-; CHECK-NEXT: .LBB7_1: @ %vector.body
+; CHECK-NEXT: .LBB8_1: @ %vector.body
; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1
; CHECK-NEXT: vldrb.u8 q0, [r0], #16
; CHECK-NEXT: vldrb.u8 q1, [r1], #16
; CHECK-NEXT: vqdmulh.s8 q0, q1, q0
; CHECK-NEXT: vstrb.8 q0, [r2], #16
-; CHECK-NEXT: le lr, .LBB7_1
+; CHECK-NEXT: le lr, .LBB8_1
; CHECK-NEXT: @ %bb.2: @ %for.cond.cleanup
; CHECK-NEXT: pop {r7, pc}
entry:
@@ -225,13 +294,13 @@ define void @vqdmulh_loop_i16(i16* nocapture readonly %x, i16* nocapture readonl
; CHECK-NEXT: push {r7, lr}
; CHECK-NEXT: mov.w lr, #128
; CHECK-NEXT: dls lr, lr
-; CHECK-NEXT: .LBB8_1: @ %vector.body
+; CHECK-NEXT: .LBB9_1: @ %vector.body
; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1
; CHECK-NEXT: vldrh.u16 q0, [r0], #16
; CHECK-NEXT: vldrh.u16 q1, [r1], #16
; CHECK-NEXT: vqdmulh.s16 q0, q1, q0
; CHECK-NEXT: vstrb.8 q0, [r2], #16
-; CHECK-NEXT: le lr, .LBB8_1
+; CHECK-NEXT: le lr, .LBB9_1
; CHECK-NEXT: @ %bb.2: @ %for.cond.cleanup
; CHECK-NEXT: pop {r7, pc}
entry:
@@ -270,13 +339,13 @@ define void @vqdmulh_loop_i32(i32* nocapture readonly %x, i32* nocapture readonl
; CHECK-NEXT: push {r7, lr}
; CHECK-NEXT: mov.w lr, #256
; CHECK-NEXT: dls lr, lr
-; CHECK-NEXT: .LBB9_1: @ %vector.body
+; CHECK-NEXT: .LBB10_1: @ %vector.body
; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1
; CHECK-NEXT: vldrw.u32 q0, [r0], #16
; CHECK-NEXT: vldrw.u32 q1, [r1], #16
; CHECK-NEXT: vqdmulh.s32 q0, q1, q0
; CHECK-NEXT: vstrb.8 q0, [r2], #16
-; CHECK-NEXT: le lr, .LBB9_1
+; CHECK-NEXT: le lr, .LBB10_1
; CHECK-NEXT: @ %bb.2: @ %for.cond.cleanup
; CHECK-NEXT: pop {r7, pc}
entry:
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