[PATCH] D94580: [RISCV] Swap encodings of max and minu to match 0.93 bitmanip spec.

[Craig Topper via Phabricator via llvm-commits]

craig.topper created this revision.
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Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D94580

Files:
  llvm/lib/Target/RISCV/RISCVInstrInfoB.td
  llvm/test/MC/RISCV/rv32zbb-valid.s


Index: llvm/test/MC/RISCV/rv32zbb-valid.s
===================================================================
--- llvm/test/MC/RISCV/rv32zbb-valid.s
+++ llvm/test/MC/RISCV/rv32zbb-valid.s
@@ -42,12 +42,12 @@
 # CHECK-ASM-AND-OBJ: min t0, t1, t2
 # CHECK-ASM: encoding: [0xb3,0x42,0x73,0x0a]
 min t0, t1, t2
-# CHECK-ASM-AND-OBJ: max t0, t1, t2
-# CHECK-ASM: encoding: [0xb3,0x52,0x73,0x0a]
-max t0, t1, t2
 # CHECK-ASM-AND-OBJ: minu t0, t1, t2
-# CHECK-ASM: encoding: [0xb3,0x62,0x73,0x0a]
+# CHECK-ASM: encoding: [0xb3,0x52,0x73,0x0a]
 minu t0, t1, t2
+# CHECK-ASM-AND-OBJ: max t0, t1, t2
+# CHECK-ASM: encoding: [0xb3,0x62,0x73,0x0a]
+max t0, t1, t2
 # CHECK-ASM-AND-OBJ: maxu t0, t1, t2
 # CHECK-ASM: encoding: [0xb3,0x72,0x73,0x0a]
 maxu t0, t1, t2
Index: llvm/lib/Target/RISCV/RISCVInstrInfoB.td
===================================================================
--- llvm/lib/Target/RISCV/RISCVInstrInfoB.td
+++ llvm/lib/Target/RISCV/RISCVInstrInfoB.td
@@ -338,8 +338,8 @@
 
 let Predicates = [HasStdExtZbb] in {
 def MIN  : ALU_rr<0b0000101, 0b100, "min">, Sched<[]>;
-def MAX  : ALU_rr<0b0000101, 0b101, "max">, Sched<[]>;
-def MINU : ALU_rr<0b0000101, 0b110, "minu">, Sched<[]>;
+def MINU : ALU_rr<0b0000101, 0b101, "minu">, Sched<[]>;
+def MAX  : ALU_rr<0b0000101, 0b110, "max">, Sched<[]>;
 def MAXU : ALU_rr<0b0000101, 0b111, "maxu">, Sched<[]>;
 } // Predicates = [HasStdExtZbb]
 


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