[PATCH] D94480: [DAGCombine] Correct the result for sqrt even the iteration is zero

[Qing Shan Zhang via Phabricator via llvm-commits]

steven.zhang created this revision.
steven.zhang added reviewers: spatel, evandro, t.p.northover, PowerPC.
Herald added subscribers: kbarton, hiraditya, kristof.beyls, nemanjai.
steven.zhang requested review of this revision.
Herald added a project: LLVM.

For now, we correct the result for sqrt if iteration > 0. This doesn't make sense as they are not strict relative. Besides, some target(i.e. AArch64 and PowerPC downstream) want to have custom sqrt soft expansion instead of the default OneConstantNR/TwoConstantNR and set the iteration as zero. We need to correct the result for them also. As AArch64 don't want to test the input with IEEE, so, I move the test implementation into the hook.

The test change is caused by the different order between FMUL and those compare instruction.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D94480

Files:
  llvm/include/llvm/CodeGen/TargetLowering.h
  llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
  llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
  llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
  llvm/lib/Target/AArch64/AArch64ISelLowering.h
  llvm/lib/Target/PowerPC/PPCISelLowering.cpp
  llvm/test/CodeGen/AArch64/sqrt-fastmath.ll

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