[PATCH] D94465: [RISCV] Frame handling for RISC-V V extension. (2nd. version)

[Jessica Clarke via Phabricator via llvm-commits]

jrtc27 added inline comments.


================
Comment at: llvm/include/llvm/CodeGen/MIRYamlMapping.h:350-351
     IO.enumCase(ID, "sgpr-spill", TargetStackID::SGPRSpill);
     IO.enumCase(ID, "sve-vec", TargetStackID::SVEVector);
+    IO.enumCase(ID, "riscv-vec", TargetStackID::RISCVVector);
     IO.enumCase(ID, "noalloc", TargetStackID::NoAlloc);
----------------
The handling of RISCVVector is always the same as SVEVector when in generic code. Can we not merge the two as they're the same thing just for different architectures?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D94465/new/

https://reviews.llvm.org/D94465