[PATCH] D94467: [PowerPC] Use mtvsrdd+vpku instructions to optimize build_vector

[Qiu Chaofan via Phabricator via llvm-commits]

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`mtvsrdd` was introduced in ISA 3.0 which moves two GPRs into a vector in single instruction. So we can use that to reduce instructions building vector from elements. Take `v8i16` as example (`u` for undef, others for elements):

  u u u a  <-- original elements
  u u u b
  ...
  
  u u u a u u u b  <-- mtvsrdd
  u u u c u u u d
  ...
  
  u a u b u c u d  <-- vpkudum
  u e u f u g u h
  
  a b c d e f g h  <-- vpkuwum

In theory, this applies for vectors from `v2i64` to `v16i8`. However, `rldimi+vpkudum` is better codegen for `v4i32`.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D94467

Files:
  llvm/lib/Target/PowerPC/PPCISelLowering.cpp
  llvm/test/CodeGen/PowerPC/pre-inc-disable.ll
  llvm/test/CodeGen/PowerPC/srem-vector-lkk.ll
  llvm/test/CodeGen/PowerPC/urem-vector-lkk.ll
  llvm/test/CodeGen/PowerPC/vec_conv_fp32_to_i16_elts.ll
  llvm/test/CodeGen/PowerPC/vec_conv_fp32_to_i8_elts.ll
  llvm/test/CodeGen/PowerPC/vec_conv_fp64_to_i16_elts.ll
  llvm/test/CodeGen/PowerPC/vec_conv_fp64_to_i8_elts.ll
  llvm/test/CodeGen/PowerPC/vec_int_ext.ll

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