[PATCH] D94457: [AArch64] Add some missing fusion subtarget features

[Cassie Jones via Phabricator via llvm-commits]

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Referencing ARM's software optimization guides:

A65 - 4.8 Instruction fusion

  Address, AES, and MOVZ/MOVK literals

A72 - 4.11 Fast literal generation

- 4.12 PC-relative address calculation

A76 - 4.6. AES Encryption/Decryption
A77/A78/A78C/X1 - 4.13 Instruction fusion

  CMP/CMN, TST, BICS + B.cond fusion
  AES fusion

[AArch64] Make Cortex B.cc fusions more precise

The ArithmeticBccFusion feature expects to be able to fuse general
flag-updating arithmetic with a B.cc, for example an arbitrary SUBS
instructions and not just a CMP.

Since the Cortex cores are documented as fusing CMP/CMN/TST, and the A77
optimization guide specifies that BICS fusion must have a destination of
XZR or WZR, these cores should use a separate subtarget feature for
specifically fusing only comparisons with B.cc.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D94457

Files:
  llvm/lib/Target/AArch64/AArch64.td
  llvm/lib/Target/AArch64/AArch64MacroFusion.cpp
  llvm/lib/Target/AArch64/AArch64Subtarget.h
  llvm/test/CodeGen/AArch64/misched-fusion-addr.ll
  llvm/test/CodeGen/AArch64/misched-fusion-aes.ll
  llvm/test/CodeGen/AArch64/misched-fusion-lit.ll

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