[PATCH] D93416: [GlobalISel] Map extractelt to G_EXTRACT_VECTOR_ELT

[Bjorn Pettersson via Phabricator via llvm-commits]

This revision was not accepted when it landed; it landed in state "Needs Review".
This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG32c073acb320: [GlobalISel] Map extractelt to G_EXTRACT_VECTOR_ELT (authored by bjope).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D93416/new/

https://reviews.llvm.org/D93416

Files:
  llvm/include/llvm/Target/GlobalISel/SelectionDAGCompat.td
  llvm/lib/Target/AArch64/AArch64InstrGISel.td
  llvm/utils/TableGen/GlobalISelEmitter.cpp


Index: llvm/utils/TableGen/GlobalISelEmitter.cpp
===================================================================
--- llvm/utils/TableGen/GlobalISelEmitter.cpp
+++ llvm/utils/TableGen/GlobalISelEmitter.cpp
@@ -4690,6 +4690,8 @@
 
   // EXTRACT_SUBREG needs to use a subregister COPY.
   if (Name == "EXTRACT_SUBREG") {
+    if (!Dst->getChild(1)->isLeaf())
+      return failedImport("EXTRACT_SUBREG child #1 is not a leaf");
     DefInit *SubRegInit = dyn_cast<DefInit>(Dst->getChild(1)->getLeafValue());
     if (!SubRegInit)
       return failedImport("EXTRACT_SUBREG child #1 is not a subreg index");
Index: llvm/lib/Target/AArch64/AArch64InstrGISel.td
===================================================================
--- llvm/lib/Target/AArch64/AArch64InstrGISel.td
+++ llvm/lib/Target/AArch64/AArch64InstrGISel.td
@@ -164,6 +164,8 @@
 def : GINodeEquiv<G_VASHR, AArch64vashr>;
 def : GINodeEquiv<G_VLSHR, AArch64vlshr>;
 
+def : GINodeEquiv<G_EXTRACT_VECTOR_ELT, vector_extract>;
+
 // These are patterns that we only use for GlobalISel via the importer.
 def : Pat<(f32 (fadd (vector_extract (v2f32 FPR64:$Rn), (i64 0)),
                      (vector_extract (v2f32 FPR64:$Rn), (i64 1)))),
Index: llvm/include/llvm/Target/GlobalISel/SelectionDAGCompat.td
===================================================================
--- llvm/include/llvm/Target/GlobalISel/SelectionDAGCompat.td
+++ llvm/include/llvm/Target/GlobalISel/SelectionDAGCompat.td
@@ -116,7 +116,7 @@
 def : GINodeEquiv<G_CTLZ_ZERO_UNDEF, ctlz_zero_undef>;
 def : GINodeEquiv<G_CTTZ_ZERO_UNDEF, cttz_zero_undef>;
 def : GINodeEquiv<G_CTPOP, ctpop>;
-def : GINodeEquiv<G_EXTRACT_VECTOR_ELT, vector_extract>;
+def : GINodeEquiv<G_EXTRACT_VECTOR_ELT, extractelt>;
 def : GINodeEquiv<G_CONCAT_VECTORS, concat_vectors>;
 def : GINodeEquiv<G_BUILD_VECTOR, build_vector>;
 def : GINodeEquiv<G_FCEIL, fceil>;


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