[PATCH] D94242: [RISCV] Add scalable vector fcmp ISel patterns

Mon Jan 11 10:55:00 PST 2021

craig.topper accepted this revision.
craig.topper added a comment.
This revision is now accepted and ready to land.

LGTM

================
Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td:361
+
+defm "" : VPatFPSetCCSDNode_VV<SETGT,  "PseudoVMFLT", /*swap*/1>;
+defm "" : VPatFPSetCCSDNode_VV<SETOGT, "PseudoVMFLT", /*swap*/1>;
----------------
frasercrmck wrote:
> craig.topper wrote:
> > frasercrmck wrote:
> > > craig.topper wrote:
> > > > What if we expanded SETGT/SETOGT/SETGE/SETOGE and pattern matched VF from the LHS of SETLT/SETOLT/SETLE/SETOLE. Would that be a net reduction in patterns since we'll lose some of the VV patterns?
> > > Possibly. Though I think I prefer it this way as it's more explicit than relying on the expansion to do what we want. Are you thinking more about wins in terms of the size of the generated tables?
> > Yeah I was trying to minimize the table size. I thought it would also make VF match easier since we would only need one pattern for each instruction except EQ/OEQ/NE/UNE. I think we already use the Expand for scalar nodes if I recall correctly.
> Good point. I have done that now: take a look. I think the table was slightly smaller (not sure how you typically measure that) in the interim, but it's a net-increase with the support for both VF and FV.
There's a comment in the RISCVGenDAGISel.inc that prints that table size. I usually just search for "bytes".

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D94242/new/

https://reviews.llvm.org/D94242