[PATCH] D94408: [RISCV] Add scalable vector fadd/fsub/fmul/fdiv ISel patterns

[Fraser Cormack via Phabricator via llvm-commits]

frasercrmck created this revision.
frasercrmck added reviewers: craig.topper, rogfer01, evandro, HsiangKai.
Herald added subscribers: NickHung, luismarques, apazos, sameer.abuasal, pzheng, s.egerton, lenary, Jim, benna, psnobl, jocewei, PkmX, the_o, brucehoult, MartinMosbeck, edward-jones, zzheng, jrtc27, shiva0217, kito-cheng, niosHD, sabuasal, simoncook, johnrusso, rbar, asb, hiraditya.
frasercrmck requested review of this revision.
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Original patch by @rogfer01.

This patch adds ISel patterns for the above operations to the
corresponding vector/vector and vector/scalar RVV instructions, as well
as extra patterns to match operand-swapped scalar/vector vfrsub and
vfrdiv.

Authored-by: Roger Ferrer Ibanez <rofirrim at gmail.com>
Co-Authored-by: Fraser Cormack <fraser at codeplay.com>


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D94408

Files:
  llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
  llvm/test/CodeGen/RISCV/rvv/vfadd-sdnode-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vfadd-sdnode-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vfdiv-sdnode-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vfdiv-sdnode-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vfmul-sdnode-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vfmul-sdnode-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vfsub-sdnode-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vfsub-sdnode-rv64.ll

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