[PATCH] D94294: [RISCV] Add scalable vector vselect ISel patterns
Fraser Cormack via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Mon Jan 11 01:59:12 PST 2021
frasercrmck marked an inline comment as done.
frasercrmck added inline comments.
================
Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td:256
+ ToFPR32<fvti.Scalar, fvti.ScalarRegClass, "rs1">.ret,
+ VMV0:$vm, VLMax, fvti.SEW)>;
+}
----------------
craig.topper wrote:
> Should we VMERGE_VIM imm 0 when the true operand is (splat_vector fpimm0)?
Yep good idea, I've done that now.
Repository:
rG LLVM Github Monorepo
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https://reviews.llvm.org/D94294/new/
https://reviews.llvm.org/D94294
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