[PATCH] D94375: [RISCV] Convert most of the information about RVV Pseudos into bits in TSFlags.

[Craig Topper via Phabricator via llvm-commits]

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This patch moves all but the BaseInstr to bits in TSFlags.

For the index fields, we can just use a bit to indicate their presence.
The locations of the operands are well defined.

This reduces the llc binary by about 32K on my build. It also
removes the binary search of the table from the custom inserter.
Instead we just check that the SEW op is present.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D94375

Files:
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/lib/Target/RISCV/RISCVInstrFormats.td
  llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
  llvm/lib/Target/RISCV/RISCVMCInstLower.cpp
  llvm/lib/Target/RISCV/Utils/RISCVBaseInfo.h

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