[PATCH] D94344: [CodeGen] Try to make the print of memory operand alignment a little more user friendly.

[Craig Topper via Phabricator via llvm-commits]

craig.topper created this revision.
craig.topper added reviewers: efriedma, arsenm, RKSimon, spatel, LemonBoy, jrtc27.
Herald added subscribers: kerbowa, pengfei, atanasyan, hiraditya, nhaehnle, jvesely, nemanjai, sdardis.
craig.topper requested review of this revision.
Herald added a subscriber: wdng.
Herald added a project: LLVM.

Memory operands store a base alignment that does not factor in
the effect of the offset on the alignment.

Previously the printing code only printed the base alignment if
it was different than the size. If there is an offset, the reader
would need to figure out the effective alignment themselves. This
has confused me before and someone else was recently confused on
IRC.

This patch prints the possibly offset adjusted alignment if it is
different than the size. And prints the base alignment if it is
different than the alignment. The MIR parser has been updated to
read basealign in addition to align.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D94344

Files:
  llvm/lib/CodeGen/MIRParser/MILexer.cpp
  llvm/lib/CodeGen/MIRParser/MILexer.h
  llvm/lib/CodeGen/MIRParser/MIParser.cpp
  llvm/lib/CodeGen/MachineOperand.cpp
  llvm/test/CodeGen/AArch64/GlobalISel/inline-memcpy.mir
  llvm/test/CodeGen/AArch64/GlobalISel/legalize-non-pow2-load-store.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-extract-vector-elt.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-insert-vector-elt.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.buffer.load.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-load.mir
  llvm/test/CodeGen/MIR/X86/memory-operands.mir
  llvm/test/CodeGen/Mips/GlobalISel/legalizer/store_split_because_of_memsize_or_align.mir
  llvm/test/CodeGen/Mips/GlobalISel/regbankselect/load.mir
  llvm/test/CodeGen/Mips/GlobalISel/regbankselect/long_ambiguous_chain_s32.mir
  llvm/test/CodeGen/Mips/GlobalISel/regbankselect/long_ambiguous_chain_s64.mir
  llvm/test/CodeGen/Mips/GlobalISel/regbankselect/store.mir
  llvm/test/CodeGen/PowerPC/aix-cc-abi.ll
  llvm/test/CodeGen/X86/avoid-sfb-offset.mir
  llvm/test/CodeGen/X86/bug47278.mir

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