[PATCH] D94294: [RISCV] Add scalable vector vselect ISel patterns

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


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Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td:256
+                 ToFPR32<fvti.Scalar, fvti.ScalarRegClass, "rs1">.ret,
+                 VMV0:$vm, VLMax, fvti.SEW)>;
+}
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Should we VMERGE_VIM imm 0 when the true operand is (splat_vector fpimm0)?


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D94294/new/

https://reviews.llvm.org/D94294