[PATCH] D94242: [RISCV] Add scalable vector fcmp ISel patterns

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


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Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td:361
+
+defm "" : VPatFPSetCCSDNode_VV<SETGT,  "PseudoVMFLT", /*swap*/1>;
+defm "" : VPatFPSetCCSDNode_VV<SETOGT, "PseudoVMFLT", /*swap*/1>;
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frasercrmck wrote:
> craig.topper wrote:
> > What if we expanded SETGT/SETOGT/SETGE/SETOGE and pattern matched VF from the LHS of SETLT/SETOLT/SETLE/SETOLE. Would that be a net reduction in patterns since we'll lose some of the VV patterns?
> Possibly. Though I think I prefer it this way as it's more explicit than relying on the expansion to do what we want. Are you thinking more about wins in terms of the size of the generated tables?
Yeah I was trying to minimize the table size. I thought it would also make VF match easier since we would only need one pattern for each instruction except EQ/OEQ/NE/UNE. I think we already use the Expand for scalar nodes if I recall correctly.


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  https://reviews.llvm.org/D94242/new/

https://reviews.llvm.org/D94242