[PATCH] D94279: [VE] Add SVOB intrinsic instruction
Kazushi Marukawa via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Fri Jan 8 01:49:36 PST 2021
This revision was automatically updated to reflect the committed changes.
Closed by commit rG12167632bc5c: [VE] Add SVOB intrinsic instruction (authored by kaz7).
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D94279/new/
https://reviews.llvm.org/D94279
Files:
llvm/include/llvm/IR/IntrinsicsVE.td
llvm/lib/Target/VE/VEInstrIntrinsicVL.td
llvm/test/CodeGen/VE/VELIntrinsics/svob.ll
Index: llvm/test/CodeGen/VE/VELIntrinsics/svob.ll
===================================================================
--- /dev/null
+++ llvm/test/CodeGen/VE/VELIntrinsics/svob.ll
@@ -0,0 +1,19 @@
+; RUN: llc < %s -mtriple=ve -mattr=+vpu | FileCheck %s
+
+;;; Test set vector out-of-order memory access boundary intrinsic instructions
+;;;
+;;; Note:
+;;; We test SVOB instruction.
+
+; Function Attrs: nounwind
+define fastcc void @svob_svob() {
+; CHECK-LABEL: svob_svob:
+; CHECK: # %bb.0:
+; CHECK-NEXT: svob
+; CHECK-NEXT: b.l.t (, %s10)
+ tail call void @llvm.ve.vl.svob()
+ ret void
+}
+
+; Function Attrs: nounwind
+declare void @llvm.ve.vl.svob()
Index: llvm/lib/Target/VE/VEInstrIntrinsicVL.td
===================================================================
--- llvm/lib/Target/VE/VEInstrIntrinsicVL.td
+++ llvm/lib/Target/VE/VEInstrIntrinsicVL.td
@@ -2,6 +2,9 @@
// Define intrinsics written by hand
+// SVOB pattern.
+def : Pat<(int_ve_vl_svob), (SVOB)>;
+
// The lsv and lvs patterns
def : Pat<(int_ve_vl_lsv_vvss v256f64:$pt, i32:$sy, i64:$sz),
(LSVrr_v (INSERT_SUBREG (i64 (IMPLICIT_DEF)), i32:$sy, sub_i32),
Index: llvm/include/llvm/IR/IntrinsicsVE.td
===================================================================
--- llvm/include/llvm/IR/IntrinsicsVE.td
+++ llvm/include/llvm/IR/IntrinsicsVE.td
@@ -1,4 +1,10 @@
// Define intrinsics written by hand
+// VEL Intrinsic instructions.
+let TargetPrefix = "ve" in {
+ def int_ve_vl_svob : GCCBuiltin<"__builtin_ve_vl_svob">,
+ Intrinsic<[], [], [IntrHasSideEffects]>;
+}
+
// Define intrinsics automatically generated
include "llvm/IR/IntrinsicsVEVL.gen.td"
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