[PATCH] D94242: [RISCV] Add scalable vector fcmp ISel patterns

[Fraser Cormack via Phabricator via llvm-commits]

frasercrmck added inline comments.


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Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td:349
+// 14.11. Vector Floating-Point Compare Instructions
+defm "" : VPatFPSetCCSDNode_VV_VF<SETEQ,  "PseudoVMFEQ">;
+defm "" : VPatFPSetCCSDNode_VV_VF<SETOEQ, "PseudoVMFEQ">;
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craig.topper wrote:
> Do we have nnan attribute tests to cover the conditions without O/U?
I'll look into that, cheers.


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Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td:361
+
+defm "" : VPatFPSetCCSDNode_VV<SETGT,  "PseudoVMFLT", /*swap*/1>;
+defm "" : VPatFPSetCCSDNode_VV<SETOGT, "PseudoVMFLT", /*swap*/1>;
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craig.topper wrote:
> What if we expanded SETGT/SETOGT/SETGE/SETOGE and pattern matched VF from the LHS of SETLT/SETOLT/SETLE/SETOLE. Would that be a net reduction in patterns since we'll lose some of the VV patterns?
Possibly. Though I think I prefer it this way as it's more explicit than relying on the expansion to do what we want. Are you thinking more about wins in terms of the size of the generated tables?


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  https://reviews.llvm.org/D94242/new/

https://reviews.llvm.org/D94242