[PATCH] D94168: [RISCV] Add scalable vector icmp ISel patterns

[Fraser Cormack via Phabricator via llvm-commits]

frasercrmck updated this revision to Diff 315157.
frasercrmck added a comment.

- improve test coverage for setcc with VX/VI on LHS
- cut down on uninteresting VI test cases to compensate


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D94168/new/

https://reviews.llvm.org/D94168

Files:
  llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
  llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
  llvm/test/CodeGen/AArch64/sve-intrinsics-int-compares-with-imm.ll
  llvm/test/CodeGen/RISCV/rvv/setcc-integer-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/setcc-integer-rv64.ll

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