[PATCH] D93599: [DAG] Simplify OR(X,SHL(Y,BW/2)) eq/ne 0/-1 'all/any-of' style patterns

[Sanjay Patel via Phabricator via llvm-commits]

spatel added inline comments.


================
Comment at: llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp:3959
+
+      // For all/any comparisons, replace or(x,shl(y,bw/2)) with and/or(x,y).
+      bool CmpZero = N1C->getAPIntValue().isNullValue();
----------------
Add an example to this comment to make it clearer which patterns we are handling:
  // When high 32-bits of i64 X are known clear:
  // all bits clear: (X | (Y<<32)) ==  0 --> (X | Y) ==  0
  // all bits set:   (X | (Y<<32)) == -1 --> (X & Y) == -1


================
Comment at: llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp:3969-3970
+          SDValue RHS = V.getOperand(1);
+          if (RHS.getOpcode() != ISD::SHL)
+            std::swap(LHS, RHS);
+          unsigned EltBits = V.getScalarValueSizeInBits();
----------------
I think we should check for the opcode + shift amount match in one shot. Otherwise, we can miss patterns that are identical other than the commuted `or` operands:

```

define i1 @shl_shl(i16 %x, i16 %y) {
  %zx = zext i16 %x to i64
  %zy = zext i16 %y to i64
  %sx = shl i64 %zx, 32
  %sy = shl i64 %zy, 8
  %or = or i64 %sx, %sy
  %r = icmp eq i64 %or, 0
  ret i1 %r
}

define i1 @shl_shl_commute(i16 %x, i16 %y) {
  %zx = zext i16 %x to i64
  %zy = zext i16 %y to i64
  %sx = shl i64 %zx, 32
  %sy = shl i64 %zy, 8
  %or = or i64 %sy, %sx
  %r = icmp eq i64 %or, 0
  ret i1 %r
}

```



Repository:
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  https://reviews.llvm.org/D93599/new/

https://reviews.llvm.org/D93599