[PATCH] D94171: [SVE][CodeGen] Fix legalisation of floating-point masked gathers

[David Sherwood via Phabricator via llvm-commits]

david-arm added inline comments.


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Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:3940
       getGatherScatterIndexIsExtended(Index) ||
+      IdxOp == AArch64ISD::UUNPKLO || IdxOp == AArch64ISD::UUNPKHI ||
+      IdxOp == AArch64ISD::SUNPKLO || IdxOp == AArch64ISD::SUNPKHI ||
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Is it worth having a helper function here, something like "isVectorUnpack(bool Signed)"? The reason I mention this is that there are two other places in the codebase where we also check if an opcode is "AArch64ISD::UUNPKLO || IdxOp == AArch64ISD::UUNPKHI".


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Comment at: llvm/test/CodeGen/AArch64/sve-masked-gather-legalize.ll:74
 
+define <vscale x 8 x half> @masked_gather_nxv8f16(<vscale x 8 x half*> %ptrs, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: masked_gather_nxv8f16:
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Is it worth having tests that load <vscale x 4 x half> as well for both the ptrs and base+offset case?


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D94171/new/

https://reviews.llvm.org/D94171