[PATCH] D94160: [AArch64][SVE] Add lowering for llvm abs intrinsic

[Paul Walker via Phabricator via llvm-commits]

paulwalker-arm accepted this revision.
paulwalker-arm added a comment.
This revision is now accepted and ready to land.

Do you plan to add support for fixed length vectors?



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Comment at: llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td:208-209
 def AArch64fabs_mt   : SDNode<"AArch64ISD::FABS_MERGE_PASSTHRU", SDT_AArch64Arith>;
+def AArch64abs_mt   : SDNode<"AArch64ISD::ABS_MERGE_PASSTHRU", SDT_AArch64Arith>;
+def AArch64neg_mt   : SDNode<"AArch64ISD::NEG_MERGE_PASSTHRU", SDT_AArch64Arith>;
 def AArch64sxt_mt    : SDNode<"AArch64ISD::SIGN_EXTEND_INREG_MERGE_PASSTHRU", SDT_AArch64IntExtend>;
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Please better align the new code.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D94160/new/

https://reviews.llvm.org/D94160