[PATCH] D94113: [PowerPC] Fix issue where vsrq is given incorrect shift vector

[Nemanja Ivanovic via Phabricator via llvm-commits]

nemanjai accepted this revision.
nemanjai added a comment.
This revision is now accepted and ready to land.

LGTM.



================
Comment at: llvm/lib/Target/PowerPC/PPCInstrPrefix.td:2561
 
+let AddedComplexity = 400, Predicates = [IsISA3_1, HasVSX] in {
+  def : Pat<(v1i128 (shl v1i128:$VRA, v1i128:$VRB)),
----------------
I know that the issue is not new with P10, but I think it would be good to mention here something like:
```
// FIXME: The swap is overkill when the shift amount is a constant.
// We should just fix the constant in the DAG.
```
And then of course, not forget to follow this patch up with one that does that :).


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https://reviews.llvm.org/D94113