[PATCH] D94073: [RISCV] Add vector integer mul/mulh/div/rem ISel patterns

[Fraser Cormack via Phabricator via llvm-commits]

frasercrmck created this revision.
frasercrmck added reviewers: craig.topper, evandro, rogfer01, HsiangKai.
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There is no test coverage for the mulhs or mulhu patterns as I can't get
the DAGCombiner to generate them for scalable vectors. There are a few
places in that still need updating for that to work. I left the patterns
in regardless as they are correct.

One caveat here is that urem on nxvXi64 vectors hits an assertion on
RV32 when SelectionDAG::getConstant needs to insert legal nodes but must
expand the i64 element type. This case cannot handle scalable vectors.

The nxvXi64 urem test cases are thus commented out for now while a fix
is thought of. The patterns are left in as they are not the ultimate
problem.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D94073

Files:
  llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
  llvm/test/CodeGen/RISCV/rvv/vdiv-sdnode-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vdiv-sdnode-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vdivu-sdnode-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vdivu-sdnode-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vmul-sdnode-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vmul-sdnode-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vrem-sdnode-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vrem-sdnode-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vremu-sdnode-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vremu-sdnode-rv64.ll

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