[PATCH] D94012: [RISCV] Add vector integer min/max ISel patterns

[Fraser Cormack via Phabricator via llvm-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rG1d4411e9ea0e: [RISCV] Add vector integer min/max ISel patterns (authored by frasercrmck).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D94012/new/

https://reviews.llvm.org/D94012

Files:
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
  llvm/test/CodeGen/RISCV/rvv/vmax-sdnode-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vmax-sdnode-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vmaxu-sdnode-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vmaxu-sdnode-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vmin-sdnode-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vmin-sdnode-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vminu-sdnode-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vminu-sdnode-rv64.ll

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