[llvm] dc9ac0e - [RISCV] Replace i32 with XLenVT in (add AddrFI, simm12) isel patterns.
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Mon Jan 4 10:54:56 PST 2021
Author: Craig Topper
Date: 2021-01-04T10:53:27-08:00
New Revision: dc9ac0e8207654e9ad57e7135276c04fdadbe36f
URL: https://github.com/llvm/llvm-project/commit/dc9ac0e8207654e9ad57e7135276c04fdadbe36f
DIFF: https://github.com/llvm/llvm-project/commit/dc9ac0e8207654e9ad57e7135276c04fdadbe36f.diff
LOG: [RISCV] Replace i32 with XLenVT in (add AddrFI, simm12) isel patterns.
With the i32 these patterns will only fire on RV32, but they
don't look RV32 specific.
Reviewed By: lenary
Differential Revision: https://reviews.llvm.org/D93843
Added:
Modified:
llvm/lib/Target/RISCV/RISCVInstrInfo.td
llvm/test/CodeGen/RISCV/vararg.ll
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.td b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
index 04e45f495e22..e31cbd37877d 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
@@ -893,10 +893,10 @@ def PseudoAddTPRel : Pseudo<(outs GPR:$rd),
/// FrameIndex calculations
-def : Pat<(add (i32 AddrFI:$Rs), simm12:$imm12),
- (ADDI (i32 AddrFI:$Rs), simm12:$imm12)>;
-def : Pat<(IsOrAdd (i32 AddrFI:$Rs), simm12:$imm12),
- (ADDI (i32 AddrFI:$Rs), simm12:$imm12)>;
+def : Pat<(add (XLenVT AddrFI:$Rs), simm12:$imm12),
+ (ADDI (XLenVT AddrFI:$Rs), simm12:$imm12)>;
+def : Pat<(IsOrAdd (XLenVT AddrFI:$Rs), simm12:$imm12),
+ (ADDI (XLenVT AddrFI:$Rs), simm12:$imm12)>;
/// Setcc
diff --git a/llvm/test/CodeGen/RISCV/vararg.ll b/llvm/test/CodeGen/RISCV/vararg.ll
index 918b1850b3a3..440f1b4a8547 100644
--- a/llvm/test/CodeGen/RISCV/vararg.ll
+++ b/llvm/test/CodeGen/RISCV/vararg.ll
@@ -108,8 +108,7 @@ define i32 @va1(i8* %fmt, ...) {
; LP64-LP64F-LP64D-FPELIM-NEXT: sd a4, 48(sp)
; LP64-LP64F-LP64D-FPELIM-NEXT: sd a3, 40(sp)
; LP64-LP64F-LP64D-FPELIM-NEXT: sd a2, 32(sp)
-; LP64-LP64F-LP64D-FPELIM-NEXT: addi a0, sp, 24
-; LP64-LP64F-LP64D-FPELIM-NEXT: ori a0, a0, 4
+; LP64-LP64F-LP64D-FPELIM-NEXT: addi a0, sp, 28
; LP64-LP64F-LP64D-FPELIM-NEXT: sd a0, 8(sp)
; LP64-LP64F-LP64D-FPELIM-NEXT: lw a0, 24(sp)
; LP64-LP64F-LP64D-FPELIM-NEXT: addi sp, sp, 80
@@ -132,8 +131,7 @@ define i32 @va1(i8* %fmt, ...) {
; LP64-LP64F-LP64D-WITHFP-NEXT: sd a4, 32(s0)
; LP64-LP64F-LP64D-WITHFP-NEXT: sd a3, 24(s0)
; LP64-LP64F-LP64D-WITHFP-NEXT: sd a2, 16(s0)
-; LP64-LP64F-LP64D-WITHFP-NEXT: addi a0, s0, 8
-; LP64-LP64F-LP64D-WITHFP-NEXT: ori a0, a0, 4
+; LP64-LP64F-LP64D-WITHFP-NEXT: addi a0, s0, 12
; LP64-LP64F-LP64D-WITHFP-NEXT: sd a0, -24(s0)
; LP64-LP64F-LP64D-WITHFP-NEXT: lw a0, 8(s0)
; LP64-LP64F-LP64D-WITHFP-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
@@ -217,8 +215,7 @@ define i32 @va1_va_arg(i8* %fmt, ...) nounwind {
; LP64-LP64F-LP64D-FPELIM-NEXT: sd a3, 40(sp)
; LP64-LP64F-LP64D-FPELIM-NEXT: sd a2, 32(sp)
; LP64-LP64F-LP64D-FPELIM-NEXT: sd a1, 24(sp)
-; LP64-LP64F-LP64D-FPELIM-NEXT: addi a1, sp, 24
-; LP64-LP64F-LP64D-FPELIM-NEXT: addi a1, a1, 8
+; LP64-LP64F-LP64D-FPELIM-NEXT: addi a1, sp, 32
; LP64-LP64F-LP64D-FPELIM-NEXT: sd a1, 8(sp)
; LP64-LP64F-LP64D-FPELIM-NEXT: addi sp, sp, 80
; LP64-LP64F-LP64D-FPELIM-NEXT: ret
@@ -237,8 +234,7 @@ define i32 @va1_va_arg(i8* %fmt, ...) nounwind {
; LP64-LP64F-LP64D-WITHFP-NEXT: sd a3, 24(s0)
; LP64-LP64F-LP64D-WITHFP-NEXT: sd a2, 16(s0)
; LP64-LP64F-LP64D-WITHFP-NEXT: sd a1, 8(s0)
-; LP64-LP64F-LP64D-WITHFP-NEXT: addi a1, s0, 8
-; LP64-LP64F-LP64D-WITHFP-NEXT: addi a1, a1, 8
+; LP64-LP64F-LP64D-WITHFP-NEXT: addi a1, s0, 16
; LP64-LP64F-LP64D-WITHFP-NEXT: sd a1, -24(s0)
; LP64-LP64F-LP64D-WITHFP-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
; LP64-LP64F-LP64D-WITHFP-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
@@ -360,8 +356,7 @@ define i32 @va1_va_arg_alloca(i8* %fmt, ...) nounwind {
; LP64-LP64F-LP64D-FPELIM-NEXT: sd a3, 24(s0)
; LP64-LP64F-LP64D-FPELIM-NEXT: sd a2, 16(s0)
; LP64-LP64F-LP64D-FPELIM-NEXT: sd a1, 8(s0)
-; LP64-LP64F-LP64D-FPELIM-NEXT: addi a0, s0, 8
-; LP64-LP64F-LP64D-FPELIM-NEXT: addi a0, a0, 8
+; LP64-LP64F-LP64D-FPELIM-NEXT: addi a0, s0, 16
; LP64-LP64F-LP64D-FPELIM-NEXT: sd a0, -32(s0)
; LP64-LP64F-LP64D-FPELIM-NEXT: slli a0, a1, 32
; LP64-LP64F-LP64D-FPELIM-NEXT: srli a0, a0, 32
@@ -396,8 +391,7 @@ define i32 @va1_va_arg_alloca(i8* %fmt, ...) nounwind {
; LP64-LP64F-LP64D-WITHFP-NEXT: sd a3, 24(s0)
; LP64-LP64F-LP64D-WITHFP-NEXT: sd a2, 16(s0)
; LP64-LP64F-LP64D-WITHFP-NEXT: sd a1, 8(s0)
-; LP64-LP64F-LP64D-WITHFP-NEXT: addi a0, s0, 8
-; LP64-LP64F-LP64D-WITHFP-NEXT: addi a0, a0, 8
+; LP64-LP64F-LP64D-WITHFP-NEXT: addi a0, s0, 16
; LP64-LP64F-LP64D-WITHFP-NEXT: sd a0, -32(s0)
; LP64-LP64F-LP64D-WITHFP-NEXT: slli a0, a1, 32
; LP64-LP64F-LP64D-WITHFP-NEXT: srli a0, a0, 32
@@ -719,8 +713,7 @@ define i64 @va2_va_arg(i8 *%fmt, ...) nounwind {
; LP64-LP64F-LP64D-FPELIM-NEXT: sd a3, 40(sp)
; LP64-LP64F-LP64D-FPELIM-NEXT: sd a2, 32(sp)
; LP64-LP64F-LP64D-FPELIM-NEXT: sd a1, 24(sp)
-; LP64-LP64F-LP64D-FPELIM-NEXT: addi a1, sp, 24
-; LP64-LP64F-LP64D-FPELIM-NEXT: addi a1, a1, 8
+; LP64-LP64F-LP64D-FPELIM-NEXT: addi a1, sp, 32
; LP64-LP64F-LP64D-FPELIM-NEXT: sd a1, 8(sp)
; LP64-LP64F-LP64D-FPELIM-NEXT: addi sp, sp, 80
; LP64-LP64F-LP64D-FPELIM-NEXT: ret
@@ -739,8 +732,7 @@ define i64 @va2_va_arg(i8 *%fmt, ...) nounwind {
; LP64-LP64F-LP64D-WITHFP-NEXT: sd a3, 24(s0)
; LP64-LP64F-LP64D-WITHFP-NEXT: sd a2, 16(s0)
; LP64-LP64F-LP64D-WITHFP-NEXT: sd a1, 8(s0)
-; LP64-LP64F-LP64D-WITHFP-NEXT: addi a1, s0, 8
-; LP64-LP64F-LP64D-WITHFP-NEXT: addi a1, a1, 8
+; LP64-LP64F-LP64D-WITHFP-NEXT: addi a1, s0, 16
; LP64-LP64F-LP64D-WITHFP-NEXT: sd a1, -24(s0)
; LP64-LP64F-LP64D-WITHFP-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
; LP64-LP64F-LP64D-WITHFP-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
@@ -1053,8 +1045,7 @@ define i64 @va3_va_arg(i32 %a, i64 %b, ...) nounwind {
; LP64-LP64F-LP64D-FPELIM-NEXT: sd a4, 32(sp)
; LP64-LP64F-LP64D-FPELIM-NEXT: sd a3, 24(sp)
; LP64-LP64F-LP64D-FPELIM-NEXT: sd a2, 16(sp)
-; LP64-LP64F-LP64D-FPELIM-NEXT: addi a0, sp, 16
-; LP64-LP64F-LP64D-FPELIM-NEXT: ori a3, a0, 8
+; LP64-LP64F-LP64D-FPELIM-NEXT: addi a3, sp, 24
; LP64-LP64F-LP64D-FPELIM-NEXT: add a0, a1, a2
; LP64-LP64F-LP64D-FPELIM-NEXT: sd a3, 8(sp)
; LP64-LP64F-LP64D-FPELIM-NEXT: addi sp, sp, 64
@@ -1072,8 +1063,7 @@ define i64 @va3_va_arg(i32 %a, i64 %b, ...) nounwind {
; LP64-LP64F-LP64D-WITHFP-NEXT: sd a4, 16(s0)
; LP64-LP64F-LP64D-WITHFP-NEXT: sd a3, 8(s0)
; LP64-LP64F-LP64D-WITHFP-NEXT: sd a2, 0(s0)
-; LP64-LP64F-LP64D-WITHFP-NEXT: mv a0, s0
-; LP64-LP64F-LP64D-WITHFP-NEXT: ori a3, a0, 8
+; LP64-LP64F-LP64D-WITHFP-NEXT: addi a3, s0, 8
; LP64-LP64F-LP64D-WITHFP-NEXT: add a0, a1, a2
; LP64-LP64F-LP64D-WITHFP-NEXT: sd a3, -24(s0)
; LP64-LP64F-LP64D-WITHFP-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
@@ -1310,8 +1300,7 @@ define i32 @va4_va_copy(i32 %argno, ...) nounwind {
; LP64-LP64F-LP64D-FPELIM-NEXT: sd a3, 56(sp)
; LP64-LP64F-LP64D-FPELIM-NEXT: sd a2, 48(sp)
; LP64-LP64F-LP64D-FPELIM-NEXT: sd a1, 40(sp)
-; LP64-LP64F-LP64D-FPELIM-NEXT: addi a0, sp, 40
-; LP64-LP64F-LP64D-FPELIM-NEXT: addi a0, a0, 8
+; LP64-LP64F-LP64D-FPELIM-NEXT: addi a0, sp, 48
; LP64-LP64F-LP64D-FPELIM-NEXT: sd a0, 8(sp)
; LP64-LP64F-LP64D-FPELIM-NEXT: sd a0, 0(sp)
; LP64-LP64F-LP64D-FPELIM-NEXT: call notdead at plt
@@ -1354,8 +1343,7 @@ define i32 @va4_va_copy(i32 %argno, ...) nounwind {
; LP64-LP64F-LP64D-WITHFP-NEXT: sd a3, 24(s0)
; LP64-LP64F-LP64D-WITHFP-NEXT: sd a2, 16(s0)
; LP64-LP64F-LP64D-WITHFP-NEXT: sd a1, 8(s0)
-; LP64-LP64F-LP64D-WITHFP-NEXT: addi a0, s0, 8
-; LP64-LP64F-LP64D-WITHFP-NEXT: addi a0, a0, 8
+; LP64-LP64F-LP64D-WITHFP-NEXT: addi a0, s0, 16
; LP64-LP64F-LP64D-WITHFP-NEXT: sd a0, -32(s0)
; LP64-LP64F-LP64D-WITHFP-NEXT: sd a0, -40(s0)
; LP64-LP64F-LP64D-WITHFP-NEXT: call notdead at plt
@@ -1717,8 +1705,7 @@ define i32 @va6_no_fixed_args(...) nounwind {
; LP64-LP64F-LP64D-FPELIM-NEXT: sd a2, 32(sp)
; LP64-LP64F-LP64D-FPELIM-NEXT: sd a1, 24(sp)
; LP64-LP64F-LP64D-FPELIM-NEXT: sd a0, 16(sp)
-; LP64-LP64F-LP64D-FPELIM-NEXT: addi a1, sp, 16
-; LP64-LP64F-LP64D-FPELIM-NEXT: ori a1, a1, 8
+; LP64-LP64F-LP64D-FPELIM-NEXT: addi a1, sp, 24
; LP64-LP64F-LP64D-FPELIM-NEXT: sd a1, 8(sp)
; LP64-LP64F-LP64D-FPELIM-NEXT: addi sp, sp, 80
; LP64-LP64F-LP64D-FPELIM-NEXT: ret
@@ -1737,8 +1724,7 @@ define i32 @va6_no_fixed_args(...) nounwind {
; LP64-LP64F-LP64D-WITHFP-NEXT: sd a2, 16(s0)
; LP64-LP64F-LP64D-WITHFP-NEXT: sd a1, 8(s0)
; LP64-LP64F-LP64D-WITHFP-NEXT: sd a0, 0(s0)
-; LP64-LP64F-LP64D-WITHFP-NEXT: mv a1, s0
-; LP64-LP64F-LP64D-WITHFP-NEXT: ori a1, a1, 8
+; LP64-LP64F-LP64D-WITHFP-NEXT: addi a1, s0, 8
; LP64-LP64F-LP64D-WITHFP-NEXT: sd a1, -24(s0)
; LP64-LP64F-LP64D-WITHFP-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
; LP64-LP64F-LP64D-WITHFP-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
@@ -1914,10 +1900,9 @@ define i32 @va_large_stack(i8* %fmt, ...) {
; LP64-LP64F-LP64D-FPELIM-NEXT: add a0, sp, a0
; LP64-LP64F-LP64D-FPELIM-NEXT: sd a2, 0(a0)
; LP64-LP64F-LP64D-FPELIM-NEXT: lui a0, 24414
-; LP64-LP64F-LP64D-FPELIM-NEXT: addiw a0, a0, 280
+; LP64-LP64F-LP64D-FPELIM-NEXT: addiw a0, a0, 284
; LP64-LP64F-LP64D-FPELIM-NEXT: add a0, sp, a0
; LP64-LP64F-LP64D-FPELIM-NEXT: mv a0, a0
-; LP64-LP64F-LP64D-FPELIM-NEXT: ori a0, a0, 4
; LP64-LP64F-LP64D-FPELIM-NEXT: sd a0, 8(sp)
; LP64-LP64F-LP64D-FPELIM-NEXT: lui a0, 24414
; LP64-LP64F-LP64D-FPELIM-NEXT: addiw a0, a0, 280
@@ -1948,8 +1933,7 @@ define i32 @va_large_stack(i8* %fmt, ...) {
; LP64-LP64F-LP64D-WITHFP-NEXT: sd a4, 32(s0)
; LP64-LP64F-LP64D-WITHFP-NEXT: sd a3, 24(s0)
; LP64-LP64F-LP64D-WITHFP-NEXT: sd a2, 16(s0)
-; LP64-LP64F-LP64D-WITHFP-NEXT: addi a0, s0, 8
-; LP64-LP64F-LP64D-WITHFP-NEXT: ori a0, a0, 4
+; LP64-LP64F-LP64D-WITHFP-NEXT: addi a0, s0, 12
; LP64-LP64F-LP64D-WITHFP-NEXT: lui a1, 1024162
; LP64-LP64F-LP64D-WITHFP-NEXT: addiw a1, a1, -288
; LP64-LP64F-LP64D-WITHFP-NEXT: add a1, s0, a1
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