[llvm] 985f899 - [Target] Use llvm::append_range (NFC)
Kazu Hirata via llvm-commits
llvm-commits at lists.llvm.org
Sun Jan 3 09:58:37 PST 2021
Author: Kazu Hirata
Date: 2021-01-03T09:57:43-08:00
New Revision: 985f899bf2cc70aeb383a46c6a84aa634677bca2
URL: https://github.com/llvm/llvm-project/commit/985f899bf2cc70aeb383a46c6a84aa634677bca2
DIFF: https://github.com/llvm/llvm-project/commit/985f899bf2cc70aeb383a46c6a84aa634677bca2.diff
LOG: [Target] Use llvm::append_range (NFC)
Added:
Modified:
llvm/lib/Target/AMDGPU/AMDGPUUnifyDivergentExitNodes.cpp
llvm/lib/Target/AMDGPU/R600MachineScheduler.cpp
llvm/lib/Target/AMDGPU/SIMachineScheduler.cpp
llvm/lib/Target/BPF/BPFAdjustOpt.cpp
llvm/lib/Target/Hexagon/HexagonCommonGEP.cpp
llvm/lib/Target/Hexagon/HexagonVectorCombine.cpp
llvm/lib/Target/X86/X86ISelLowering.cpp
llvm/lib/Target/X86/X86InstrInfo.cpp
Removed:
################################################################################
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUUnifyDivergentExitNodes.cpp b/llvm/lib/Target/AMDGPU/AMDGPUUnifyDivergentExitNodes.cpp
index 9ea8b3265b0d..7232548bbb85 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUUnifyDivergentExitNodes.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUUnifyDivergentExitNodes.cpp
@@ -392,8 +392,7 @@ bool AMDGPUUnifyDivergentExitNodes::runOnFunction(Function &F) {
// uniformly reached block with the "done" bit cleared.
auto BlocksToUnify = std::move(ReturningBlocks);
if (InsertExport) {
- BlocksToUnify.insert(BlocksToUnify.end(), UniformlyReachedRetBlocks.begin(),
- UniformlyReachedRetBlocks.end());
+ llvm::append_range(BlocksToUnify, UniformlyReachedRetBlocks);
}
unifyReturnBlockSet(F, DTU, BlocksToUnify, InsertExport, TTI,
diff --git a/llvm/lib/Target/AMDGPU/R600MachineScheduler.cpp b/llvm/lib/Target/AMDGPU/R600MachineScheduler.cpp
index d7d53c644f33..7382c2f076e4 100644
--- a/llvm/lib/Target/AMDGPU/R600MachineScheduler.cpp
+++ b/llvm/lib/Target/AMDGPU/R600MachineScheduler.cpp
@@ -45,7 +45,7 @@ void R600SchedStrategy::initialize(ScheduleDAGMI *dag) {
void R600SchedStrategy::MoveUnits(std::vector<SUnit *> &QSrc,
std::vector<SUnit *> &QDst)
{
- QDst.insert(QDst.end(), QSrc.begin(), QSrc.end());
+ llvm::append_range(QDst, QSrc);
QSrc.clear();
}
diff --git a/llvm/lib/Target/AMDGPU/SIMachineScheduler.cpp b/llvm/lib/Target/AMDGPU/SIMachineScheduler.cpp
index a8b607618946..ee119ff71e96 100644
--- a/llvm/lib/Target/AMDGPU/SIMachineScheduler.cpp
+++ b/llvm/lib/Target/AMDGPU/SIMachineScheduler.cpp
@@ -763,8 +763,7 @@ void SIScheduleBlockCreator::colorHighLatenciesGroups() {
// depend (order dependency) on one of the
// instruction in the block, and are required for the
// high latency instruction we add.
- AdditionalElements.insert(AdditionalElements.end(),
- SubGraph.begin(), SubGraph.end());
+ llvm::append_range(AdditionalElements, SubGraph);
}
}
if (CompatibleGroup) {
diff --git a/llvm/lib/Target/BPF/BPFAdjustOpt.cpp b/llvm/lib/Target/BPF/BPFAdjustOpt.cpp
index 928b591b2274..da543e7eba53 100644
--- a/llvm/lib/Target/BPF/BPFAdjustOpt.cpp
+++ b/llvm/lib/Target/BPF/BPFAdjustOpt.cpp
@@ -301,7 +301,7 @@ bool BPFAdjustOptImpl::avoidSpeculation(Instruction &I) {
if (!isCandidate || Candidates.empty())
return false;
- PassThroughs.insert(PassThroughs.end(), Candidates.begin(), Candidates.end());
+ llvm::append_range(PassThroughs, Candidates);
return true;
}
diff --git a/llvm/lib/Target/Hexagon/HexagonCommonGEP.cpp b/llvm/lib/Target/Hexagon/HexagonCommonGEP.cpp
index 04cd432f56c5..11e7d5a17fa9 100644
--- a/llvm/lib/Target/Hexagon/HexagonCommonGEP.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonCommonGEP.cpp
@@ -447,7 +447,7 @@ static void nodes_for_root(GepNode *Root, NodeChildrenMap &NCM,
Work.erase(First);
NodeChildrenMap::iterator CF = NCM.find(N);
if (CF != NCM.end()) {
- Work.insert(Work.end(), CF->second.begin(), CF->second.end());
+ llvm::append_range(Work, CF->second);
Nodes.insert(CF->second.begin(), CF->second.end());
}
}
@@ -1145,7 +1145,7 @@ void HexagonCommonGEP::getAllUsersForNode(GepNode *Node, ValueVect &Values,
NodeChildrenMap::iterator CF = NCM.find(N);
if (CF != NCM.end()) {
NodeVect &Cs = CF->second;
- Work.insert(Work.end(), Cs.begin(), Cs.end());
+ llvm::append_range(Work, Cs);
}
}
}
diff --git a/llvm/lib/Target/Hexagon/HexagonVectorCombine.cpp b/llvm/lib/Target/Hexagon/HexagonVectorCombine.cpp
index 52b0a1a58c19..056a5a83a0a6 100644
--- a/llvm/lib/Target/Hexagon/HexagonVectorCombine.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonVectorCombine.cpp
@@ -585,7 +585,7 @@ auto AlignVectors::createLoadGroups(const AddrList &Group) const -> MoveList {
if (llvm::any_of(Deps, inAddrMap))
return false;
Move.Main.push_back(Info.Inst);
- Move.Deps.insert(Move.Deps.end(), Deps.begin(), Deps.end());
+ llvm::append_range(Move.Deps, Deps);
return true;
};
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index 811318054fe1..4dce5283b2ab 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -3513,8 +3513,7 @@ void VarArgsLoweringHelper::createVarArgAreaAndStoreRegisters(
DAG.getTargetConstant(FuncInfo->getRegSaveFrameIndex(), DL, MVT::i32));
SaveXMMOps.push_back(
DAG.getTargetConstant(FuncInfo->getVarArgsFPOffset(), DL, MVT::i32));
- SaveXMMOps.insert(SaveXMMOps.end(), LiveXMMRegs.begin(),
- LiveXMMRegs.end());
+ llvm::append_range(SaveXMMOps, LiveXMMRegs);
MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, DL,
MVT::Other, SaveXMMOps));
}
diff --git a/llvm/lib/Target/X86/X86InstrInfo.cpp b/llvm/lib/Target/X86/X86InstrInfo.cpp
index 57eac4080cbb..d9bab14f0c08 100644
--- a/llvm/lib/Target/X86/X86InstrInfo.cpp
+++ b/llvm/lib/Target/X86/X86InstrInfo.cpp
@@ -6464,7 +6464,7 @@ X86InstrInfo::unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
}
if (Load)
BeforeOps.push_back(SDValue(Load, 0));
- BeforeOps.insert(BeforeOps.end(), AfterOps.begin(), AfterOps.end());
+ llvm::append_range(BeforeOps, AfterOps);
// Change CMP32ri r, 0 back to TEST32rr r, r, etc.
switch (Opc) {
default: break;
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