[llvm] f7f42e6 - [TableGen] Use llvm::append_range (NFC)
Kazu Hirata via llvm-commits
llvm-commits at lists.llvm.org
Sat Jan 2 09:24:58 PST 2021
Author: Kazu Hirata
Date: 2021-01-02T09:24:13-08:00
New Revision: f7f42e64dfa287479e97fb0ddd3212b953622819
URL: https://github.com/llvm/llvm-project/commit/f7f42e64dfa287479e97fb0ddd3212b953622819
DIFF: https://github.com/llvm/llvm-project/commit/f7f42e64dfa287479e97fb0ddd3212b953622819.diff
LOG: [TableGen] Use llvm::append_range (NFC)
Added:
Modified:
llvm/utils/TableGen/CodeGenDAGPatterns.cpp
llvm/utils/TableGen/CodeGenSchedule.cpp
llvm/utils/TableGen/CodeGenTarget.cpp
llvm/utils/TableGen/FixedLenDecoderEmitter.cpp
llvm/utils/TableGen/RegisterInfoEmitter.cpp
llvm/utils/TableGen/SubtargetEmitter.cpp
llvm/utils/TableGen/WebAssemblyDisassemblerEmitter.cpp
Removed:
################################################################################
diff --git a/llvm/utils/TableGen/CodeGenDAGPatterns.cpp b/llvm/utils/TableGen/CodeGenDAGPatterns.cpp
index e098f632c80a..6b6e1ec7b04d 100644
--- a/llvm/utils/TableGen/CodeGenDAGPatterns.cpp
+++ b/llvm/utils/TableGen/CodeGenDAGPatterns.cpp
@@ -4293,7 +4293,7 @@ void CodeGenDAGPatterns::ExpandHwModeBasedTypes() {
std::vector<Predicate> Preds = P.Predicates;
const std::vector<Predicate> &MC = ModeChecks[Mode];
- Preds.insert(Preds.end(), MC.begin(), MC.end());
+ llvm::append_range(Preds, MC);
PatternsToMatch.emplace_back(P.getSrcRecord(), Preds, std::move(NewSrc),
std::move(NewDst), P.getDstRegs(),
P.getAddedComplexity(), Record::getNewUID(),
diff --git a/llvm/utils/TableGen/CodeGenSchedule.cpp b/llvm/utils/TableGen/CodeGenSchedule.cpp
index 8b54ff0d1d72..3210a60d9de2 100644
--- a/llvm/utils/TableGen/CodeGenSchedule.cpp
+++ b/llvm/utils/TableGen/CodeGenSchedule.cpp
@@ -1549,8 +1549,7 @@ pushVariant(const TransVariant &VInfo, bool IsRead) {
ExpandedRWs.push_back(*RWI);
else
SchedModels.expandRWSequence(*RWI, ExpandedRWs, IsRead);
- RWSequences[OperIdx].insert(RWSequences[OperIdx].end(),
- ExpandedRWs.begin(), ExpandedRWs.end());
+ llvm::append_range(RWSequences[OperIdx], ExpandedRWs);
}
assert(OperIdx == RWSequences.size() && "missed a sequence");
}
@@ -1566,7 +1565,7 @@ pushVariant(const TransVariant &VInfo, bool IsRead) {
else
SchedModels.expandRWSequence(*RWI, ExpandedRWs, IsRead);
}
- Seq.insert(Seq.end(), ExpandedRWs.begin(), ExpandedRWs.end());
+ llvm::append_range(Seq, ExpandedRWs);
}
}
@@ -1826,8 +1825,7 @@ void CodeGenSchedModels::verifyProcResourceGroups(CodeGenProcModel &PM) {
OtherUnits.begin(), OtherUnits.end())
!= CheckUnits.end()) {
// CheckUnits and OtherUnits overlap
- OtherUnits.insert(OtherUnits.end(), CheckUnits.begin(),
- CheckUnits.end());
+ llvm::append_range(OtherUnits, CheckUnits);
if (!hasSuperGroup(OtherUnits, PM)) {
PrintFatalError((PM.ProcResourceDefs[i])->getLoc(),
"proc resource group overlaps with "
diff --git a/llvm/utils/TableGen/CodeGenTarget.cpp b/llvm/utils/TableGen/CodeGenTarget.cpp
index 2cfcd1820cc1..37bce3afa05a 100644
--- a/llvm/utils/TableGen/CodeGenTarget.cpp
+++ b/llvm/utils/TableGen/CodeGenTarget.cpp
@@ -403,7 +403,7 @@ std::vector<ValueTypeByHwMode> CodeGenTarget::getRegisterVTs(Record *R)
for (const auto &RC : getRegBank().getRegClasses()) {
if (RC.contains(Reg)) {
ArrayRef<ValueTypeByHwMode> InVTs = RC.getValueTypes();
- Result.insert(Result.end(), InVTs.begin(), InVTs.end());
+ llvm::append_range(Result, InVTs);
}
}
@@ -416,7 +416,7 @@ std::vector<ValueTypeByHwMode> CodeGenTarget::getRegisterVTs(Record *R)
void CodeGenTarget::ReadLegalValueTypes() const {
for (const auto &RC : getRegBank().getRegClasses())
- LegalValueTypes.insert(LegalValueTypes.end(), RC.VTs.begin(), RC.VTs.end());
+ llvm::append_range(LegalValueTypes, RC.VTs);
// Remove duplicates.
llvm::sort(LegalValueTypes);
diff --git a/llvm/utils/TableGen/FixedLenDecoderEmitter.cpp b/llvm/utils/TableGen/FixedLenDecoderEmitter.cpp
index 6a7db45c6bde..4f1f559f99f0 100644
--- a/llvm/utils/TableGen/FixedLenDecoderEmitter.cpp
+++ b/llvm/utils/TableGen/FixedLenDecoderEmitter.cpp
@@ -722,7 +722,7 @@ void Filter::emitTableEntry(DecoderTableInfo &TableInfo) const {
assert(TableInfo.FixupStack.size() > 1 && "fixup stack underflow!");
FixupScopeList::iterator Source = TableInfo.FixupStack.end() - 1;
FixupScopeList::iterator Dest = Source - 1;
- Dest->insert(Dest->end(), Source->begin(), Source->end());
+ llvm::append_range(*Dest, *Source);
TableInfo.FixupStack.pop_back();
// If there is no fallthrough, then the final filter should get fixed
@@ -2010,9 +2010,8 @@ populateInstruction(CodeGenTarget &Target, const Record &EncodingDef,
// For each operand, see if we can figure out where it is encoded.
for (const auto &Op : InOutOperands) {
if (!NumberedInsnOperands[std::string(Op.second)].empty()) {
- InsnOperands.insert(InsnOperands.end(),
- NumberedInsnOperands[std::string(Op.second)].begin(),
- NumberedInsnOperands[std::string(Op.second)].end());
+ llvm::append_range(InsnOperands,
+ NumberedInsnOperands[std::string(Op.second)]);
continue;
}
if (!NumberedInsnOperands[TiedNames[std::string(Op.second)]].empty()) {
diff --git a/llvm/utils/TableGen/RegisterInfoEmitter.cpp b/llvm/utils/TableGen/RegisterInfoEmitter.cpp
index 63710a1ae658..38809b495c64 100644
--- a/llvm/utils/TableGen/RegisterInfoEmitter.cpp
+++ b/llvm/utils/TableGen/RegisterInfoEmitter.cpp
@@ -960,7 +960,7 @@ RegisterInfoEmitter::runMCDesc(raw_ostream &OS, CodeGenTarget &Target,
const auto &RUMasks = Reg.getRegUnitLaneMasks();
MaskVec &LaneMaskVec = RegUnitLaneMasks[i];
assert(LaneMaskVec.empty());
- LaneMaskVec.insert(LaneMaskVec.begin(), RUMasks.begin(), RUMasks.end());
+ llvm::append_range(LaneMaskVec, RUMasks);
// Terminator mask should not be used inside of the list.
#ifndef NDEBUG
for (LaneBitmask M : LaneMaskVec) {
diff --git a/llvm/utils/TableGen/SubtargetEmitter.cpp b/llvm/utils/TableGen/SubtargetEmitter.cpp
index 9cb25af28018..bd40d0e83dec 100644
--- a/llvm/utils/TableGen/SubtargetEmitter.cpp
+++ b/llvm/utils/TableGen/SubtargetEmitter.cpp
@@ -1220,11 +1220,8 @@ void SubtargetEmitter::GenSchedClassTables(const CodeGenProcModel &ProcModel,
}
else {
SCDesc.WriteLatencyIdx = SchedTables.WriteLatencies.size();
- SchedTables.WriteLatencies.insert(SchedTables.WriteLatencies.end(),
- WriteLatencies.begin(),
- WriteLatencies.end());
- SchedTables.WriterNames.insert(SchedTables.WriterNames.end(),
- WriterNames.begin(), WriterNames.end());
+ llvm::append_range(SchedTables.WriteLatencies, WriteLatencies);
+ llvm::append_range(SchedTables.WriterNames, WriterNames);
}
// ReadAdvanceEntries must remain in operand order.
SCDesc.NumReadAdvanceEntries = ReadAdvanceEntries.size();
@@ -1236,8 +1233,7 @@ void SubtargetEmitter::GenSchedClassTables(const CodeGenProcModel &ProcModel,
SCDesc.ReadAdvanceIdx = RAPos - SchedTables.ReadAdvanceEntries.begin();
else {
SCDesc.ReadAdvanceIdx = SchedTables.ReadAdvanceEntries.size();
- SchedTables.ReadAdvanceEntries.insert(RAPos, ReadAdvanceEntries.begin(),
- ReadAdvanceEntries.end());
+ llvm::append_range(SchedTables.ReadAdvanceEntries, ReadAdvanceEntries);
}
}
}
diff --git a/llvm/utils/TableGen/WebAssemblyDisassemblerEmitter.cpp b/llvm/utils/TableGen/WebAssemblyDisassemblerEmitter.cpp
index 037e852a452d..7518b262e6e9 100644
--- a/llvm/utils/TableGen/WebAssemblyDisassemblerEmitter.cpp
+++ b/llvm/utils/TableGen/WebAssemblyDisassemblerEmitter.cpp
@@ -139,8 +139,7 @@ void emitWebAssemblyDisassemblerTables(
}
// Store operands if no prior occurrence.
if (OperandStart == OperandTable.size()) {
- OperandTable.insert(OperandTable.end(), CurOperandList.begin(),
- CurOperandList.end());
+ llvm::append_range(OperandTable, CurOperandList);
}
OS << OperandStart;
} else {
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