[llvm] a64b89e - [ARM][test] Add explicit dso_local to definitions in ELF static relocation model tests
Fangrui Song via llvm-commits
llvm-commits at lists.llvm.org
Wed Dec 30 15:23:28 PST 2020
Author: Fangrui Song
Date: 2020-12-30T15:23:21-08:00
New Revision: a64b89e69e3e3d9884e135082a80b6010e127219
URL: https://github.com/llvm/llvm-project/commit/a64b89e69e3e3d9884e135082a80b6010e127219
DIFF: https://github.com/llvm/llvm-project/commit/a64b89e69e3e3d9884e135082a80b6010e127219.diff
LOG: [ARM][test] Add explicit dso_local to definitions in ELF static relocation model tests
TargetMachine::shouldAssumeDSOLocal currently implies dso_local for such definitions.
Adding explicit dso_local makes these tests align with the clang -fno-pic behavior
and allow the removal of the TargetMachine::shouldAssumeDSOLocal special case.
Added:
Modified:
llvm/test/CodeGen/ARM/aeabi-read-tp.ll
llvm/test/CodeGen/ARM/cortex-a57-misched-ldm-wrback.ll
llvm/test/CodeGen/ARM/cortex-a57-misched-vldm-wrback.ll
llvm/test/CodeGen/ARM/cortex-a57-misched-vstm-wrback.ll
llvm/test/CodeGen/ARM/fast-isel-pie.ll
llvm/test/CodeGen/ARM/global-merge-alignment.ll
llvm/test/CodeGen/ARM/global-merge-external-2.ll
llvm/test/CodeGen/ARM/global-merge-external.ll
llvm/test/CodeGen/ARM/ldm-base-writeback.ll
llvm/test/CodeGen/ARM/pie.ll
llvm/test/CodeGen/ARM/tls1.ll
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/ARM/aeabi-read-tp.ll b/llvm/test/CodeGen/ARM/aeabi-read-tp.ll
index 5f9815b6cd77..d15755a837fc 100644
--- a/llvm/test/CodeGen/ARM/aeabi-read-tp.ll
+++ b/llvm/test/CodeGen/ARM/aeabi-read-tp.ll
@@ -3,9 +3,9 @@
; RUN: llc -mtriple armv7---eabi -mattr=+long-calls -filetype asm -o - %s | FileCheck %s -check-prefix CHECK -check-prefix CHECK-LONG
; RUN: llc -mtriple thumbv7---eabi -mattr=+long-calls -filetype asm -o - %s | FileCheck %s -check-prefix CHECK -check-prefix CHECK-LONG
- at i = thread_local local_unnamed_addr global i32 0, align 4
+ at i = dso_local thread_local local_unnamed_addr global i32 0, align 4
-define i32 @f() local_unnamed_addr {
+define dso_local i32 @f() local_unnamed_addr {
entry:
%0 = load i32, i32* @i, align 4
ret i32 %0
diff --git a/llvm/test/CodeGen/ARM/cortex-a57-misched-ldm-wrback.ll b/llvm/test/CodeGen/ARM/cortex-a57-misched-ldm-wrback.ll
index be3df4aae506..ddcd72d9d67a 100644
--- a/llvm/test/CodeGen/ARM/cortex-a57-misched-ldm-wrback.ll
+++ b/llvm/test/CodeGen/ARM/cortex-a57-misched-ldm-wrback.ll
@@ -2,9 +2,9 @@
; RUN: llc < %s -mtriple=armv8r-eabi -mcpu=cortex-a57 -mattr=use-misched -verify-misched -debug-only=machine-scheduler -o - 2>&1 > /dev/null | FileCheck %s
;
- at a = global i32 0, align 4
- at b = global i32 0, align 4
- at c = global i32 0, align 4
+ at a = dso_local global i32 0, align 4
+ at b = dso_local global i32 0, align 4
+ at c = dso_local global i32 0, align 4
; CHECK: ********** MI Scheduling **********
; We need second, post-ra scheduling to have LDM instruction combined from single-loads
@@ -21,7 +21,7 @@
; CHECK-SAME: Latency=0
; CHECK-NEXT: Data
; CHECK-SAME: Latency=0
-define i32 @bar(i32 %a1, i32 %b1, i32 %c1) minsize optsize {
+define dso_local i32 @bar(i32 %a1, i32 %b1, i32 %c1) minsize optsize {
%1 = load i32, i32* @a, align 4
%2 = load i32, i32* @b, align 4
%3 = load i32, i32* @c, align 4
diff --git a/llvm/test/CodeGen/ARM/cortex-a57-misched-vldm-wrback.ll b/llvm/test/CodeGen/ARM/cortex-a57-misched-vldm-wrback.ll
index 88b772cc294e..bf923eab4c89 100644
--- a/llvm/test/CodeGen/ARM/cortex-a57-misched-vldm-wrback.ll
+++ b/llvm/test/CodeGen/ARM/cortex-a57-misched-vldm-wrback.ll
@@ -2,9 +2,9 @@
; RUN: llc < %s -mtriple=armv8r-eabi -mcpu=cortex-a57 -mattr=use-misched -verify-misched -debug-only=machine-scheduler -o - 2>&1 > /dev/null | FileCheck %s
;
- at a = global double 0.0, align 4
- at b = global double 0.0, align 4
- at c = global double 0.0, align 4
+ at a = dso_local global double 0.0, align 4
+ at b = dso_local global double 0.0, align 4
+ at c = dso_local global double 0.0, align 4
; CHECK: ********** MI Scheduling **********
; We need second, post-ra scheduling to have VLDM instruction combined from single-loads
@@ -23,7 +23,7 @@
; CHECK-SAME: Latency=0
; CHECK-NEXT: Data
; CHECK-SAME: Latency=0
-define i32 @bar(i32* %iptr) minsize optsize {
+define dso_local i32 @bar(i32* %iptr) minsize optsize {
%1 = load double, double* @a, align 8
%2 = load double, double* @b, align 8
%3 = load double, double* @c, align 8
diff --git a/llvm/test/CodeGen/ARM/cortex-a57-misched-vstm-wrback.ll b/llvm/test/CodeGen/ARM/cortex-a57-misched-vstm-wrback.ll
index c517f46e5614..afa43eac95c7 100644
--- a/llvm/test/CodeGen/ARM/cortex-a57-misched-vstm-wrback.ll
+++ b/llvm/test/CodeGen/ARM/cortex-a57-misched-vstm-wrback.ll
@@ -12,11 +12,11 @@
; CHECK: Data
; CHECK-SAME: Latency=1
- at a = global double 0.0, align 4
- at b = global double 0.0, align 4
- at c = global double 0.0, align 4
+ at a = dso_local global double 0.0, align 4
+ at b = dso_local global double 0.0, align 4
+ at c = dso_local global double 0.0, align 4
-define i32 @bar(double* %vptr, i32 %iv1, i32* %iptr) minsize {
+define dso_local i32 @bar(double* %vptr, i32 %iv1, i32* %iptr) minsize {
%vp2 = getelementptr double, double* %vptr, i32 1
%vp3 = getelementptr double, double* %vptr, i32 2
diff --git a/llvm/test/CodeGen/ARM/fast-isel-pie.ll b/llvm/test/CodeGen/ARM/fast-isel-pie.ll
index 23a88bdaa22e..0d9b4ae198aa 100644
--- a/llvm/test/CodeGen/ARM/fast-isel-pie.ll
+++ b/llvm/test/CodeGen/ARM/fast-isel-pie.ll
@@ -1,8 +1,8 @@
; RUN: llc < %s -O0 -fast-isel-abort=1 -relocation-model=pic -mtriple=armv7-pc-linux-gnueabi | FileCheck %s
- at var = global i32 42
+ at var = dso_local global i32 42
-define i32* @foo() {
+define dso_local i32* @foo() {
; CHECK: foo:
; CHECK: ldr r0, .L[[POOL:.*]]
; CHECK-NEXT: .L[[ADDR:.*]]:
diff --git a/llvm/test/CodeGen/ARM/global-merge-alignment.ll b/llvm/test/CodeGen/ARM/global-merge-alignment.ll
index 83e3c92fc089..2e4ee065bfc8 100644
--- a/llvm/test/CodeGen/ARM/global-merge-alignment.ll
+++ b/llvm/test/CodeGen/ARM/global-merge-alignment.ll
@@ -3,8 +3,8 @@
target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"
target triple = "thumbv7em-arm-none-eabi"
- at f = local_unnamed_addr global [4 x i32*] zeroinitializer, align 4
- at d = local_unnamed_addr global i64 0, align 8
+ at f = dso_local local_unnamed_addr global [4 x i32*] zeroinitializer, align 4
+ at d = dso_local local_unnamed_addr global i64 0, align 8
;CHECK: .section .bss..L_MergedGlobals,"aw",%nobits
;CHECK-NEXT: .p2align 3
@@ -13,7 +13,7 @@ target triple = "thumbv7em-arm-none-eabi"
;CHECK-NEXT: .size .L_MergedGlobals, 24
-define i32 @func_1() {
+define dso_local i32 @func_1() {
%1 = load i64, i64* @d, align 8
%2 = load i32*, i32** getelementptr inbounds ([4 x i32*], [4 x i32*]* @f, i32 0, i32 0), align 4
%3 = load i32, i32* %2, align 4
diff --git a/llvm/test/CodeGen/ARM/global-merge-external-2.ll b/llvm/test/CodeGen/ARM/global-merge-external-2.ll
index 0abca99e6b82..e0945e91b4d0 100644
--- a/llvm/test/CodeGen/ARM/global-merge-external-2.ll
+++ b/llvm/test/CodeGen/ARM/global-merge-external-2.ll
@@ -5,16 +5,16 @@
; RUN: llc < %s -mtriple=arm-eabi -arm-global-merge -relocation-model=pic | FileCheck %s --check-prefixes=CHECK,CHECK-NO-MERGE
; RUN: llc < %s -mtriple=thumbv7-win32 -arm-global-merge | FileCheck %s --check-prefixes=CHECK-WIN32
- at x = global i32 0, align 4
- at y = global i32 0, align 4
+ at x = dso_local global i32 0, align 4
+ at y = dso_local global i32 0, align 4
@z = internal global i32 1, align 4
-define void @f1(i32 %a1, i32 %a2) {
+define dso_local void @f1(i32 %a1, i32 %a2) {
;CHECK: f1:
;CHECK: ldr {{r[0-9]+}}, [[LABEL1:\.?LCPI[0-9]+_[0-9]]]
;CHECK: [[LABEL1]]:
;CHECK-MERGE: .long .L_MergedGlobals
-;CHECK-NO-MERGE: .long {{_?x}}
+;CHECK-NO-MERGE: .long {{_?x|.L_MergedGlobals}}
;CHECK-WIN32: f1:
;CHECK-WIN32: movw [[REG1:r[0-9]+]], :lower16:.L_MergedGlobals
;CHECK-WIN32: movt [[REG1]], :upper16:.L_MergedGlobals
@@ -23,7 +23,7 @@ define void @f1(i32 %a1, i32 %a2) {
ret void
}
-define void @g1(i32 %a1, i32 %a2) {
+define dso_local void @g1(i32 %a1, i32 %a2) {
;CHECK: g1:
;CHECK: ldr {{r[0-9]+}}, [[LABEL2:\.?LCPI[0-9]+_[0-9]]]
;CHECK: ldr {{r[0-9]+}}, [[LABEL3:\.?LCPI[0-9]+_[0-9]]]
@@ -31,7 +31,7 @@ define void @g1(i32 %a1, i32 %a2) {
;CHECK-MERGE: .long {{_?z}}
;CHECK: [[LABEL3]]:
;CHECK-MERGE: .long .L_MergedGlobals
-;CHECK-NO-MERGE: .long {{_?y}}
+;CHECK-NO-MERGE: .long {{_?y|.L_MergedGlobals}}
;CHECK-WIN32: g1:
;CHECK-WIN32: movw [[REG2:r[0-9]+]], :lower16:z
;CHECK-WIN32: movt [[REG2]], :upper16:z
diff --git a/llvm/test/CodeGen/ARM/global-merge-external.ll b/llvm/test/CodeGen/ARM/global-merge-external.ll
index 9834836d2b7b..f6796a2b0558 100644
--- a/llvm/test/CodeGen/ARM/global-merge-external.ll
+++ b/llvm/test/CodeGen/ARM/global-merge-external.ll
@@ -5,16 +5,16 @@
; RUN: llc < %s -mtriple=arm-eabi -arm-global-merge -relocation-model=pic | FileCheck %s --check-prefixes=CHECK,CHECK-NO-MERGE
; RUN: llc < %s -mtriple=thumbv7-win32 -arm-global-merge | FileCheck %s --check-prefixes=CHECK-WIN32
- at x = global i32 0, align 4
- at y = global i32 0, align 4
- at z = global i32 0, align 4
+ at x = dso_local global i32 0, align 4
+ at y = dso_local global i32 0, align 4
+ at z = dso_local global i32 0, align 4
-define void @f1(i32 %a1, i32 %a2) {
+define dso_local void @f1(i32 %a1, i32 %a2) {
;CHECK: f1:
;CHECK: ldr {{r[0-9]+}}, [[LABEL1:\.?LCPI[0-9]+_[0-9]]]
;CHECK: [[LABEL1]]:
;CHECK-MERGE: .long .L_MergedGlobals
-;CHECK-NO-MERGE: .long {{_?x}}
+;CHECK-NO-MERGE: .long {{_?x|.L_MergedGlobals}}
;CHECK-WIN32: f1:
;CHECK-WIN32: movw [[REG1:r[0-9]+]], :lower16:.L_MergedGlobals
;CHECK-WIN32: movt [[REG1]], :upper16:.L_MergedGlobals
@@ -23,12 +23,12 @@ define void @f1(i32 %a1, i32 %a2) {
ret void
}
-define void @g1(i32 %a1, i32 %a2) {
+define dso_local void @g1(i32 %a1, i32 %a2) {
;CHECK: g1:
;CHECK: ldr {{r[0-9]+}}, [[LABEL2:\.?LCPI[0-9]+_[0-9]]]
;CHECK: [[LABEL2]]:
;CHECK-MERGE: .long .L_MergedGlobals
-;CHECK-NO-MERGE: .long {{_?y}}
+;CHECK-NO-MERGE: .long {{_?y|.L_MergedGlobals}}
;CHECK-WIN32: g1:
;CHECK-WIN32: movw [[REG2:r[0-9]+]], :lower16:.L_MergedGlobals
;CHECK-WIN32: movt [[REG2]], :upper16:.L_MergedGlobals
diff --git a/llvm/test/CodeGen/ARM/ldm-base-writeback.ll b/llvm/test/CodeGen/ARM/ldm-base-writeback.ll
index 375f58a24a19..4c2ff7bbbba1 100644
--- a/llvm/test/CodeGen/ARM/ldm-base-writeback.ll
+++ b/llvm/test/CodeGen/ARM/ldm-base-writeback.ll
@@ -3,13 +3,13 @@
target datalayout = "e-m:e-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"
target triple = "armv7--linux-gnu"
- at a = global i32 0, align 4
- at b = global i32 0, align 4
- at c = global i32 0, align 4
+ at a = dso_local global i32 0, align 4
+ at b = dso_local global i32 0, align 4
+ at c = dso_local global i32 0, align 4
; CHECK-LABEL: bar:
; CHECK: ldm r{{[0-9]}}!, {r0, r{{[0-9]}}, r{{[0-9]}}}
-define void @bar(i32 %a1, i32 %b1, i32 %c1) minsize optsize {
+define dso_local void @bar(i32 %a1, i32 %b1, i32 %c1) minsize optsize {
%1 = load i32, i32* @a, align 4
%2 = load i32, i32* @b, align 4
%3 = load i32, i32* @c, align 4
diff --git a/llvm/test/CodeGen/ARM/pie.ll b/llvm/test/CodeGen/ARM/pie.ll
index 1b1e6e62fda5..ced5bb362f33 100644
--- a/llvm/test/CodeGen/ARM/pie.ll
+++ b/llvm/test/CodeGen/ARM/pie.ll
@@ -1,8 +1,8 @@
; RUN: llc -mtriple=armv7-pc-linux-gnueabi -relocation-model=pic < %s | FileCheck %s
- at foo = global i32 42
+ at foo = dso_local global i32 42
-define i32* @get_foo() {
+define dso_local i32* @get_foo() {
ret i32* @foo
}
diff --git a/llvm/test/CodeGen/ARM/tls1.ll b/llvm/test/CodeGen/ARM/tls1.ll
index 496d3339d684..7e26800724f0 100644
--- a/llvm/test/CodeGen/ARM/tls1.ll
+++ b/llvm/test/CodeGen/ARM/tls1.ll
@@ -8,15 +8,15 @@
; PIC: __tls_get_addr
- at i = thread_local global i32 15 ; <i32*> [#uses=2]
+ at i = dso_local thread_local global i32 15 ; <i32*> [#uses=2]
-define i32 @f() {
+define dso_local i32 @f() {
entry:
%tmp1 = load i32, i32* @i ; <i32> [#uses=1]
ret i32 %tmp1
}
-define i32* @g() {
+define dso_local i32* @g() {
entry:
ret i32* @i
}
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