[llvm] 871de4a - [X86][test] Add explicit dso_local to definitions in ELF static relocation model tests
Fangrui Song via llvm-commits
llvm-commits at lists.llvm.org
Wed Dec 30 14:40:59 PST 2020
Author: Fangrui Song
Date: 2020-12-30T14:40:50-08:00
New Revision: 871de4a479c80e9ea9040c95ff0a22b3a21c36be
URL: https://github.com/llvm/llvm-project/commit/871de4a479c80e9ea9040c95ff0a22b3a21c36be
DIFF: https://github.com/llvm/llvm-project/commit/871de4a479c80e9ea9040c95ff0a22b3a21c36be.diff
LOG: [X86][test] Add explicit dso_local to definitions in ELF static relocation model tests
TargetMachine::shouldAssumeDSOLocal currently implies dso_local for such definitions.
Adding explicit dso_local makes these tests align with the clang -fno-pic behavior
and allow the removal of the TargetMachine::shouldAssumeDSOLocal special case.
Added:
Modified:
llvm/test/CodeGen/X86/2007-01-13-StackPtrIndex.ll
llvm/test/CodeGen/X86/2010-08-04-MaskedSignedCompare.ll
llvm/test/CodeGen/X86/2011-10-19-LegelizeLoad.ll
llvm/test/CodeGen/X86/GlobalISel/GV.ll
llvm/test/CodeGen/X86/GlobalISel/select-GV-32.mir
llvm/test/CodeGen/X86/GlobalISel/select-GV-64.mir
llvm/test/CodeGen/X86/abi-isel.ll
llvm/test/CodeGen/X86/atomic-fp.ll
llvm/test/CodeGen/X86/avx-vzeroupper.ll
llvm/test/CodeGen/X86/avx2-gather.ll
llvm/test/CodeGen/X86/avx512-gather-scatter-intrin.ll
llvm/test/CodeGen/X86/avx512-regcall-Mask.ll
llvm/test/CodeGen/X86/avx512-regcall-NoMask.ll
llvm/test/CodeGen/X86/backpropmask.ll
llvm/test/CodeGen/X86/break-false-dep.ll
llvm/test/CodeGen/X86/bswap.ll
llvm/test/CodeGen/X86/callbr-asm-branch-folding.ll
llvm/test/CodeGen/X86/cast-vsel.ll
llvm/test/CodeGen/X86/cmov-double.ll
llvm/test/CodeGen/X86/cmovcmov.ll
llvm/test/CodeGen/X86/cmp.ll
llvm/test/CodeGen/X86/copy-eflags.ll
llvm/test/CodeGen/X86/critical-edge-split-2.ll
llvm/test/CodeGen/X86/dbg-changes-codegen.ll
llvm/test/CodeGen/X86/emutls-pie.ll
llvm/test/CodeGen/X86/emutls.ll
llvm/test/CodeGen/X86/fmf-flags.ll
llvm/test/CodeGen/X86/fp128-cast-strict.ll
llvm/test/CodeGen/X86/fp128-cast.ll
llvm/test/CodeGen/X86/fp128-g.ll
llvm/test/CodeGen/X86/fp128-i128.ll
llvm/test/CodeGen/X86/fp128-libcalls.ll
llvm/test/CodeGen/X86/fp128-load.ll
llvm/test/CodeGen/X86/fp128-store.ll
llvm/test/CodeGen/X86/ga-offset.ll
llvm/test/CodeGen/X86/global-access-pie.ll
llvm/test/CodeGen/X86/hoist-spill-lpad.ll
llvm/test/CodeGen/X86/immediate_merging.ll
llvm/test/CodeGen/X86/inline-asm-h.ll
llvm/test/CodeGen/X86/lea-recursion.ll
llvm/test/CodeGen/X86/linux-preemption.ll
llvm/test/CodeGen/X86/load-partial.ll
llvm/test/CodeGen/X86/lsr-sort.ll
llvm/test/CodeGen/X86/mempcpy.ll
llvm/test/CodeGen/X86/min-legal-vector-width.ll
llvm/test/CodeGen/X86/ms-inline-asm-PR44272.ll
llvm/test/CodeGen/X86/musttail-tailcc.ll
llvm/test/CodeGen/X86/narrow_op-1.ll
llvm/test/CodeGen/X86/peephole-fold-movsd.ll
llvm/test/CodeGen/X86/pie.ll
llvm/test/CodeGen/X86/pr22774.ll
llvm/test/CodeGen/X86/pr31956.ll
llvm/test/CodeGen/X86/pr32282.ll
llvm/test/CodeGen/X86/pr33290.ll
llvm/test/CodeGen/X86/pr34629.ll
llvm/test/CodeGen/X86/pr34634.ll
llvm/test/CodeGen/X86/pr35761.ll
llvm/test/CodeGen/X86/pr35763.ll
llvm/test/CodeGen/X86/pr35765.ll
llvm/test/CodeGen/X86/pr36312.ll
llvm/test/CodeGen/X86/pr37826.ll
llvm/test/CodeGen/X86/pr38217.ll
llvm/test/CodeGen/X86/pr38803.ll
llvm/test/CodeGen/X86/pr38865.ll
llvm/test/CodeGen/X86/pr43866.ll
llvm/test/CodeGen/X86/rd-mod-wr-eflags.ll
llvm/test/CodeGen/X86/sad.ll
llvm/test/CodeGen/X86/shift-combine.ll
llvm/test/CodeGen/X86/shrink-compare-pgso.ll
llvm/test/CodeGen/X86/shrink-compare.ll
llvm/test/CodeGen/X86/sibcall.ll
llvm/test/CodeGen/X86/speculative-execution-side-effect-suppression.ll
llvm/test/CodeGen/X86/speculative-load-hardening-indirect.ll
llvm/test/CodeGen/X86/splat-for-size.ll
llvm/test/CodeGen/X86/stores-merging.ll
llvm/test/CodeGen/X86/subvector-broadcast.ll
llvm/test/CodeGen/X86/swift-return.ll
llvm/test/CodeGen/X86/tail-opts.ll
llvm/test/CodeGen/X86/tailcall-disable.ll
llvm/test/CodeGen/X86/tailcall-tailcc.ll
llvm/test/CodeGen/X86/tailcall.ll
llvm/test/CodeGen/X86/test-shrink-bug.ll
llvm/test/CodeGen/X86/tls-pie.ll
llvm/test/CodeGen/X86/tls.ll
llvm/test/CodeGen/X86/trunc-and.ll
llvm/test/CodeGen/X86/undef-label.ll
llvm/test/CodeGen/X86/vec-loadsingles-alignment.ll
llvm/test/CodeGen/X86/widen_load-1.ll
llvm/test/CodeGen/X86/x86-64-intrcc.ll
llvm/test/CodeGen/X86/xor-select-i1-combine.ll
llvm/test/CodeGen/X86/xray-tail-call-sled.ll
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/X86/2007-01-13-StackPtrIndex.ll b/llvm/test/CodeGen/X86/2007-01-13-StackPtrIndex.ll
index db668b8e0a22..b231a258e9d1 100644
--- a/llvm/test/CodeGen/X86/2007-01-13-StackPtrIndex.ll
+++ b/llvm/test/CodeGen/X86/2007-01-13-StackPtrIndex.ll
@@ -3,10 +3,10 @@
; PR1103
target datalayout = "e-p:64:64"
- at i6000 = global [128 x i64] zeroinitializer, align 16
+ at i6000 = dso_local global [128 x i64] zeroinitializer, align 16
-define void @foo(i32* %a0, i32* %a1, i32* %a2, i32* %a3, i32* %a4, i32* %a5) {
+define dso_local void @foo(i32* %a0, i32* %a1, i32* %a2, i32* %a3, i32* %a4, i32* %a5) {
; CHECK-LABEL: foo:
; CHECK: # %bb.0: # %b
; CHECK-NEXT: pushq %rbp
diff --git a/llvm/test/CodeGen/X86/2010-08-04-MaskedSignedCompare.ll b/llvm/test/CodeGen/X86/2010-08-04-MaskedSignedCompare.ll
index e7793e83b01c..63b575487b40 100644
--- a/llvm/test/CodeGen/X86/2010-08-04-MaskedSignedCompare.ll
+++ b/llvm/test/CodeGen/X86/2010-08-04-MaskedSignedCompare.ll
@@ -2,11 +2,11 @@
; RUN: llc < %s -mtriple=x86_64-unknown-unknown | FileCheck %s
; PR7814
- at g_16 = global i64 -3738643449681751625, align 8
- at g_38 = global i32 0, align 4
+ at g_16 = dso_local global i64 -3738643449681751625, align 8
+ at g_38 = dso_local global i32 0, align 4
@.str = private constant [4 x i8] c"%d\0A\00"
-define i32 @main() nounwind {
+define dso_local i32 @main() nounwind {
; CHECK-LABEL: main:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: pushq %rax
diff --git a/llvm/test/CodeGen/X86/2011-10-19-LegelizeLoad.ll b/llvm/test/CodeGen/X86/2011-10-19-LegelizeLoad.ll
index 2fd61879c163..5578d2e897fd 100644
--- a/llvm/test/CodeGen/X86/2011-10-19-LegelizeLoad.ll
+++ b/llvm/test/CodeGen/X86/2011-10-19-LegelizeLoad.ll
@@ -6,15 +6,15 @@ target triple = "x86_64-unknown-linux-gnu"
%union.anon = type { <2 x i8> }
- at i = global <2 x i8> <i8 150, i8 100>, align 8
- at j = global <2 x i8> <i8 10, i8 13>, align 8
- at res = common global %union.anon zeroinitializer, align 8
+ at i = dso_local global <2 x i8> <i8 150, i8 100>, align 8
+ at j = dso_local global <2 x i8> <i8 10, i8 13>, align 8
+ at res = common dso_local global %union.anon zeroinitializer, align 8
; Make sure we load the constants i and j starting offset zero.
; Also make sure that we sign-extend it.
; Based on /gcc-4_2-testsuite/src/gcc.c-torture/execute/pr23135.c
-define i32 @main() nounwind uwtable {
+define dso_local i32 @main() nounwind uwtable {
; CHECK-LABEL: main:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: movq {{.*}}(%rip), %rsi
diff --git a/llvm/test/CodeGen/X86/GlobalISel/GV.ll b/llvm/test/CodeGen/X86/GlobalISel/GV.ll
index 09a2fe665c40..0e333ea12010 100644
--- a/llvm/test/CodeGen/X86/GlobalISel/GV.ll
+++ b/llvm/test/CodeGen/X86/GlobalISel/GV.ll
@@ -4,10 +4,10 @@
; RUN: llc -mtriple=i386-linux-gnu -global-isel -verify-machineinstrs < %s -o - | FileCheck %s --check-prefix=X32
; RUN: llc -mtriple=x86_64-linux-gnux32 -global-isel -verify-machineinstrs < %s -o - | FileCheck %s --check-prefix=X32ABI
- at g_int = global i32 0, align 4
+ at g_int = dso_local global i32 0, align 4
; Function Attrs: noinline nounwind optnone uwtable
-define i32* @test_global_ptrv() #3 {
+define dso_local i32* @test_global_ptrv() #3 {
; X64-LABEL: test_global_ptrv:
; X64: # %bb.0: # %entry
; X64-NEXT: leaq g_int, %rax
@@ -32,7 +32,7 @@ entry:
}
; Function Attrs: noinline nounwind optnone uwtable
-define i32 @test_global_valv() #3 {
+define dso_local i32 @test_global_valv() #3 {
; X64-LABEL: test_global_valv:
; X64: # %bb.0: # %entry
; X64-NEXT: leaq g_int, %rax
diff --git a/llvm/test/CodeGen/X86/GlobalISel/select-GV-32.mir b/llvm/test/CodeGen/X86/GlobalISel/select-GV-32.mir
index 7d61e1c3f052..348d1cd40a1b 100644
--- a/llvm/test/CodeGen/X86/GlobalISel/select-GV-32.mir
+++ b/llvm/test/CodeGen/X86/GlobalISel/select-GV-32.mir
@@ -3,15 +3,15 @@
--- |
- @g_int = global i32 0, align 4
+ @g_int = dso_local global i32 0, align 4
- define void @test_global_ptrv() {
+ define dso_local void @test_global_ptrv() {
entry:
store i32* @g_int, i32** undef
ret void
}
- define i32 @test_global_valv() {
+ define dso_local i32 @test_global_valv() {
entry:
%0 = load i32, i32* @g_int, align 4
ret i32 %0
diff --git a/llvm/test/CodeGen/X86/GlobalISel/select-GV-64.mir b/llvm/test/CodeGen/X86/GlobalISel/select-GV-64.mir
index ce3f0ca611b8..48c98d72325a 100644
--- a/llvm/test/CodeGen/X86/GlobalISel/select-GV-64.mir
+++ b/llvm/test/CodeGen/X86/GlobalISel/select-GV-64.mir
@@ -3,15 +3,15 @@
--- |
- @g_int = global i32 0, align 4
+ @g_int = dso_local global i32 0, align 4
- define void @test_global_ptrv() {
+ define dso_local void @test_global_ptrv() {
entry:
store i32* @g_int, i32** undef
ret void
}
- define i32 @test_global_valv() {
+ define dso_local i32 @test_global_valv() {
entry:
%0 = load i32, i32* @g_int, align 4
ret i32 %0
diff --git a/llvm/test/CodeGen/X86/abi-isel.ll b/llvm/test/CodeGen/X86/abi-isel.ll
index 170e597d7498..16a832c3ed9b 100644
--- a/llvm/test/CodeGen/X86/abi-isel.ll
+++ b/llvm/test/CodeGen/X86/abi-isel.ll
@@ -19,21 +19,21 @@
@xsrc = external global [32 x i32]
@xdst = external global [32 x i32]
@ptr = external global i32*
- at dsrc = global [131072 x i32] zeroinitializer, align 32
- at ddst = global [131072 x i32] zeroinitializer, align 32
- at dptr = global i32* null
+ at dsrc = dso_local global [131072 x i32] zeroinitializer, align 32
+ at ddst = dso_local global [131072 x i32] zeroinitializer, align 32
+ at dptr = dso_local global i32* null
@lsrc = internal global [131072 x i32] zeroinitializer
@ldst = internal global [131072 x i32] zeroinitializer
@lptr = internal global i32* null
@ifunc = external global void ()*
- at difunc = global void ()* null
+ at difunc = dso_local global void ()* null
@lifunc = internal global void ()* null
@lxsrc = internal global [32 x i32] zeroinitializer, align 32
@lxdst = internal global [32 x i32] zeroinitializer, align 32
- at dxsrc = global [32 x i32] zeroinitializer, align 32
- at dxdst = global [32 x i32] zeroinitializer, align 32
+ at dxsrc = dso_local global [32 x i32] zeroinitializer, align 32
+ at dxdst = dso_local global [32 x i32] zeroinitializer, align 32
-define void @foo00() nounwind {
+define dso_local void @foo00() nounwind {
; LINUX-64-STATIC-LABEL: foo00:
; LINUX-64-STATIC: # %bb.0: # %entry
; LINUX-64-STATIC-NEXT: movq src@{{.*}}(%rip), %rax
@@ -125,7 +125,7 @@ entry:
}
-define void @fxo00() nounwind {
+define dso_local void @fxo00() nounwind {
; LINUX-64-STATIC-LABEL: fxo00:
; LINUX-64-STATIC: # %bb.0: # %entry
; LINUX-64-STATIC-NEXT: movq xsrc@{{.*}}(%rip), %rax
@@ -217,7 +217,7 @@ entry:
}
-define void @foo01() nounwind {
+define dso_local void @foo01() nounwind {
; LINUX-64-STATIC-LABEL: foo01:
; LINUX-64-STATIC: # %bb.0: # %entry
; LINUX-64-STATIC-NEXT: movq dst@{{.*}}(%rip), %rax
@@ -297,7 +297,7 @@ entry:
ret void
}
-define void @fxo01() nounwind {
+define dso_local void @fxo01() nounwind {
; LINUX-64-STATIC-LABEL: fxo01:
; LINUX-64-STATIC: # %bb.0: # %entry
; LINUX-64-STATIC-NEXT: movq xdst@{{.*}}(%rip), %rax
@@ -377,7 +377,7 @@ entry:
ret void
}
-define void @foo02() nounwind {
+define dso_local void @foo02() nounwind {
; LINUX-64-STATIC-LABEL: foo02:
; LINUX-64-STATIC: # %bb.0: # %entry
; LINUX-64-STATIC-NEXT: movq src@{{.*}}(%rip), %rax
@@ -479,7 +479,7 @@ entry:
ret void
}
-define void @fxo02() nounwind {
+define dso_local void @fxo02() nounwind {
; LINUX-64-STATIC-LABEL: fxo02:
; LINUX-64-STATIC: # %bb.0: # %entry
; LINUX-64-STATIC-NEXT: movq xsrc@{{.*}}(%rip), %rax
@@ -581,7 +581,7 @@ entry:
ret void
}
-define void @foo03() nounwind {
+define dso_local void @foo03() nounwind {
; LINUX-64-STATIC-LABEL: foo03:
; LINUX-64-STATIC: # %bb.0: # %entry
; LINUX-64-STATIC-NEXT: movl {{.*}}(%rip), %eax
@@ -601,18 +601,14 @@ define void @foo03() nounwind {
; LINUX-32-PIC-NEXT: popl %eax
; LINUX-32-PIC-NEXT: .Ltmp6:
; LINUX-32-PIC-NEXT: addl $_GLOBAL_OFFSET_TABLE_+(.Ltmp6-.L6$pb), %eax
-; LINUX-32-PIC-NEXT: movl dsrc at GOT(%eax), %ecx
-; LINUX-32-PIC-NEXT: movl (%ecx), %ecx
-; LINUX-32-PIC-NEXT: movl ddst at GOT(%eax), %eax
-; LINUX-32-PIC-NEXT: movl %ecx, (%eax)
+; LINUX-32-PIC-NEXT: movl .Ldsrc$local at GOTOFF(%eax), %ecx
+; LINUX-32-PIC-NEXT: movl %ecx, .Lddst$local at GOTOFF(%eax)
; LINUX-32-PIC-NEXT: retl
;
; LINUX-64-PIC-LABEL: foo03:
; LINUX-64-PIC: # %bb.0: # %entry
-; LINUX-64-PIC-NEXT: movq dsrc@{{.*}}(%rip), %rax
-; LINUX-64-PIC-NEXT: movl (%rax), %eax
-; LINUX-64-PIC-NEXT: movq ddst@{{.*}}(%rip), %rcx
-; LINUX-64-PIC-NEXT: movl %eax, (%rcx)
+; LINUX-64-PIC-NEXT: movl .Ldsrc${{.*}}(%rip), %eax
+; LINUX-64-PIC-NEXT: movl %eax, .Lddst${{.*}}(%rip)
; LINUX-64-PIC-NEXT: retq
;
; DARWIN-32-STATIC-LABEL: foo03:
@@ -660,7 +656,7 @@ entry:
ret void
}
-define void @foo04() nounwind {
+define dso_local void @foo04() nounwind {
; LINUX-64-STATIC-LABEL: foo04:
; LINUX-64-STATIC: # %bb.0: # %entry
; LINUX-64-STATIC-NEXT: movq $ddst, {{.*}}(%rip)
@@ -678,16 +674,14 @@ define void @foo04() nounwind {
; LINUX-32-PIC-NEXT: popl %eax
; LINUX-32-PIC-NEXT: .Ltmp7:
; LINUX-32-PIC-NEXT: addl $_GLOBAL_OFFSET_TABLE_+(.Ltmp7-.L7$pb), %eax
-; LINUX-32-PIC-NEXT: movl ddst at GOT(%eax), %ecx
-; LINUX-32-PIC-NEXT: movl dptr at GOT(%eax), %eax
-; LINUX-32-PIC-NEXT: movl %ecx, (%eax)
+; LINUX-32-PIC-NEXT: leal .Lddst$local at GOTOFF(%eax), %ecx
+; LINUX-32-PIC-NEXT: movl %ecx, .Ldptr$local at GOTOFF(%eax)
; LINUX-32-PIC-NEXT: retl
;
; LINUX-64-PIC-LABEL: foo04:
; LINUX-64-PIC: # %bb.0: # %entry
-; LINUX-64-PIC-NEXT: movq ddst@{{.*}}(%rip), %rax
-; LINUX-64-PIC-NEXT: movq dptr@{{.*}}(%rip), %rcx
-; LINUX-64-PIC-NEXT: movq %rax, (%rcx)
+; LINUX-64-PIC-NEXT: leaq .Lddst${{.*}}(%rip), %rax
+; LINUX-64-PIC-NEXT: movq %rax, .Ldptr${{.*}}(%rip)
; LINUX-64-PIC-NEXT: retq
;
; DARWIN-32-STATIC-LABEL: foo04:
@@ -732,7 +726,7 @@ entry:
ret void
}
-define void @foo05() nounwind {
+define dso_local void @foo05() nounwind {
; LINUX-64-STATIC-LABEL: foo05:
; LINUX-64-STATIC: # %bb.0: # %entry
; LINUX-64-STATIC-NEXT: movl {{.*}}(%rip), %eax
@@ -754,19 +748,15 @@ define void @foo05() nounwind {
; LINUX-32-PIC-NEXT: popl %eax
; LINUX-32-PIC-NEXT: .Ltmp8:
; LINUX-32-PIC-NEXT: addl $_GLOBAL_OFFSET_TABLE_+(.Ltmp8-.L8$pb), %eax
-; LINUX-32-PIC-NEXT: movl dsrc at GOT(%eax), %ecx
-; LINUX-32-PIC-NEXT: movl (%ecx), %ecx
-; LINUX-32-PIC-NEXT: movl dptr at GOT(%eax), %eax
-; LINUX-32-PIC-NEXT: movl (%eax), %eax
+; LINUX-32-PIC-NEXT: movl .Ldsrc$local at GOTOFF(%eax), %ecx
+; LINUX-32-PIC-NEXT: movl .Ldptr$local at GOTOFF(%eax), %eax
; LINUX-32-PIC-NEXT: movl %ecx, (%eax)
; LINUX-32-PIC-NEXT: retl
;
; LINUX-64-PIC-LABEL: foo05:
; LINUX-64-PIC: # %bb.0: # %entry
-; LINUX-64-PIC-NEXT: movq dsrc@{{.*}}(%rip), %rax
-; LINUX-64-PIC-NEXT: movl (%rax), %eax
-; LINUX-64-PIC-NEXT: movq dptr@{{.*}}(%rip), %rcx
-; LINUX-64-PIC-NEXT: movq (%rcx), %rcx
+; LINUX-64-PIC-NEXT: movl .Ldsrc${{.*}}(%rip), %eax
+; LINUX-64-PIC-NEXT: movq .Ldptr${{.*}}(%rip), %rcx
; LINUX-64-PIC-NEXT: movl %eax, (%rcx)
; LINUX-64-PIC-NEXT: retq
;
@@ -822,7 +812,7 @@ entry:
ret void
}
-define void @foo06() nounwind {
+define dso_local void @foo06() nounwind {
; LINUX-64-STATIC-LABEL: foo06:
; LINUX-64-STATIC: # %bb.0: # %entry
; LINUX-64-STATIC-NEXT: movl {{.*}}(%rip), %eax
@@ -897,7 +887,7 @@ entry:
ret void
}
-define void @foo07() nounwind {
+define dso_local void @foo07() nounwind {
; LINUX-64-STATIC-LABEL: foo07:
; LINUX-64-STATIC: # %bb.0: # %entry
; LINUX-64-STATIC-NEXT: movq $ldst, {{.*}}(%rip)
@@ -967,7 +957,7 @@ entry:
ret void
}
-define void @foo08() nounwind {
+define dso_local void @foo08() nounwind {
; LINUX-64-STATIC-LABEL: foo08:
; LINUX-64-STATIC: # %bb.0: # %entry
; LINUX-64-STATIC-NEXT: movl {{.*}}(%rip), %eax
@@ -1053,7 +1043,7 @@ entry:
ret void
}
-define void @qux00() nounwind {
+define dso_local void @qux00() nounwind {
; LINUX-64-STATIC-LABEL: qux00:
; LINUX-64-STATIC: # %bb.0: # %entry
; LINUX-64-STATIC-NEXT: movq src@{{.*}}(%rip), %rax
@@ -1144,7 +1134,7 @@ entry:
ret void
}
-define void @qxx00() nounwind {
+define dso_local void @qxx00() nounwind {
; LINUX-64-STATIC-LABEL: qxx00:
; LINUX-64-STATIC: # %bb.0: # %entry
; LINUX-64-STATIC-NEXT: movq xsrc@{{.*}}(%rip), %rax
@@ -1235,7 +1225,7 @@ entry:
ret void
}
-define void @qux01() nounwind {
+define dso_local void @qux01() nounwind {
; LINUX-64-STATIC-LABEL: qux01:
; LINUX-64-STATIC: # %bb.0: # %entry
; LINUX-64-STATIC-NEXT: movq dst@{{.*}}(%rip), %rax
@@ -1324,7 +1314,7 @@ entry:
ret void
}
-define void @qxx01() nounwind {
+define dso_local void @qxx01() nounwind {
; LINUX-64-STATIC-LABEL: qxx01:
; LINUX-64-STATIC: # %bb.0: # %entry
; LINUX-64-STATIC-NEXT: movq xdst@{{.*}}(%rip), %rax
@@ -1413,7 +1403,7 @@ entry:
ret void
}
-define void @qux02() nounwind {
+define dso_local void @qux02() nounwind {
; LINUX-64-STATIC-LABEL: qux02:
; LINUX-64-STATIC: # %bb.0: # %entry
; LINUX-64-STATIC-NEXT: movq src@{{.*}}(%rip), %rax
@@ -1516,7 +1506,7 @@ entry:
ret void
}
-define void @qxx02() nounwind {
+define dso_local void @qxx02() nounwind {
; LINUX-64-STATIC-LABEL: qxx02:
; LINUX-64-STATIC: # %bb.0: # %entry
; LINUX-64-STATIC-NEXT: movq xsrc@{{.*}}(%rip), %rax
@@ -1619,7 +1609,7 @@ entry:
ret void
}
-define void @qux03() nounwind {
+define dso_local void @qux03() nounwind {
; LINUX-64-STATIC-LABEL: qux03:
; LINUX-64-STATIC: # %bb.0: # %entry
; LINUX-64-STATIC-NEXT: movl dsrc+{{.*}}(%rip), %eax
@@ -1639,18 +1629,14 @@ define void @qux03() nounwind {
; LINUX-32-PIC-NEXT: popl %eax
; LINUX-32-PIC-NEXT: .Ltmp18:
; LINUX-32-PIC-NEXT: addl $_GLOBAL_OFFSET_TABLE_+(.Ltmp18-.L18$pb), %eax
-; LINUX-32-PIC-NEXT: movl dsrc at GOT(%eax), %ecx
-; LINUX-32-PIC-NEXT: movl 64(%ecx), %ecx
-; LINUX-32-PIC-NEXT: movl ddst at GOT(%eax), %eax
-; LINUX-32-PIC-NEXT: movl %ecx, 64(%eax)
+; LINUX-32-PIC-NEXT: movl .Ldsrc$local at GOTOFF+64(%eax), %ecx
+; LINUX-32-PIC-NEXT: movl %ecx, .Lddst$local at GOTOFF+64(%eax)
; LINUX-32-PIC-NEXT: retl
;
; LINUX-64-PIC-LABEL: qux03:
; LINUX-64-PIC: # %bb.0: # %entry
-; LINUX-64-PIC-NEXT: movq dsrc@{{.*}}(%rip), %rax
-; LINUX-64-PIC-NEXT: movl 64(%rax), %eax
-; LINUX-64-PIC-NEXT: movq ddst@{{.*}}(%rip), %rcx
-; LINUX-64-PIC-NEXT: movl %eax, 64(%rcx)
+; LINUX-64-PIC-NEXT: movl .Ldsrc$local+{{.*}}(%rip), %eax
+; LINUX-64-PIC-NEXT: movl %eax, .Lddst$local+{{.*}}(%rip)
; LINUX-64-PIC-NEXT: retq
;
; DARWIN-32-STATIC-LABEL: qux03:
@@ -1698,7 +1684,7 @@ entry:
ret void
}
-define void @qux04() nounwind {
+define dso_local void @qux04() nounwind {
; LINUX-64-STATIC-LABEL: qux04:
; LINUX-64-STATIC: # %bb.0: # %entry
; LINUX-64-STATIC-NEXT: movq $ddst+64, {{.*}}(%rip)
@@ -1716,18 +1702,14 @@ define void @qux04() nounwind {
; LINUX-32-PIC-NEXT: popl %eax
; LINUX-32-PIC-NEXT: .Ltmp19:
; LINUX-32-PIC-NEXT: addl $_GLOBAL_OFFSET_TABLE_+(.Ltmp19-.L19$pb), %eax
-; LINUX-32-PIC-NEXT: movl ddst at GOT(%eax), %ecx
-; LINUX-32-PIC-NEXT: addl $64, %ecx
-; LINUX-32-PIC-NEXT: movl dptr at GOT(%eax), %eax
-; LINUX-32-PIC-NEXT: movl %ecx, (%eax)
+; LINUX-32-PIC-NEXT: leal .Lddst$local at GOTOFF+64(%eax), %ecx
+; LINUX-32-PIC-NEXT: movl %ecx, .Ldptr$local at GOTOFF(%eax)
; LINUX-32-PIC-NEXT: retl
;
; LINUX-64-PIC-LABEL: qux04:
; LINUX-64-PIC: # %bb.0: # %entry
-; LINUX-64-PIC-NEXT: movq ddst@{{.*}}(%rip), %rax
-; LINUX-64-PIC-NEXT: addq $64, %rax
-; LINUX-64-PIC-NEXT: movq dptr@{{.*}}(%rip), %rcx
-; LINUX-64-PIC-NEXT: movq %rax, (%rcx)
+; LINUX-64-PIC-NEXT: leaq .Lddst$local+{{.*}}(%rip), %rax
+; LINUX-64-PIC-NEXT: movq %rax, .Ldptr${{.*}}(%rip)
; LINUX-64-PIC-NEXT: retq
;
; DARWIN-32-STATIC-LABEL: qux04:
@@ -1772,7 +1754,7 @@ entry:
ret void
}
-define void @qux05() nounwind {
+define dso_local void @qux05() nounwind {
; LINUX-64-STATIC-LABEL: qux05:
; LINUX-64-STATIC: # %bb.0: # %entry
; LINUX-64-STATIC-NEXT: movl dsrc+{{.*}}(%rip), %eax
@@ -1794,19 +1776,15 @@ define void @qux05() nounwind {
; LINUX-32-PIC-NEXT: popl %eax
; LINUX-32-PIC-NEXT: .Ltmp20:
; LINUX-32-PIC-NEXT: addl $_GLOBAL_OFFSET_TABLE_+(.Ltmp20-.L20$pb), %eax
-; LINUX-32-PIC-NEXT: movl dsrc at GOT(%eax), %ecx
-; LINUX-32-PIC-NEXT: movl 64(%ecx), %ecx
-; LINUX-32-PIC-NEXT: movl dptr at GOT(%eax), %eax
-; LINUX-32-PIC-NEXT: movl (%eax), %eax
+; LINUX-32-PIC-NEXT: movl .Ldsrc$local at GOTOFF+64(%eax), %ecx
+; LINUX-32-PIC-NEXT: movl .Ldptr$local at GOTOFF(%eax), %eax
; LINUX-32-PIC-NEXT: movl %ecx, 64(%eax)
; LINUX-32-PIC-NEXT: retl
;
; LINUX-64-PIC-LABEL: qux05:
; LINUX-64-PIC: # %bb.0: # %entry
-; LINUX-64-PIC-NEXT: movq dsrc@{{.*}}(%rip), %rax
-; LINUX-64-PIC-NEXT: movl 64(%rax), %eax
-; LINUX-64-PIC-NEXT: movq dptr@{{.*}}(%rip), %rcx
-; LINUX-64-PIC-NEXT: movq (%rcx), %rcx
+; LINUX-64-PIC-NEXT: movl .Ldsrc$local+{{.*}}(%rip), %eax
+; LINUX-64-PIC-NEXT: movq .Ldptr${{.*}}(%rip), %rcx
; LINUX-64-PIC-NEXT: movl %eax, 64(%rcx)
; LINUX-64-PIC-NEXT: retq
;
@@ -1863,7 +1841,7 @@ entry:
ret void
}
-define void @qux06() nounwind {
+define dso_local void @qux06() nounwind {
; LINUX-64-STATIC-LABEL: qux06:
; LINUX-64-STATIC: # %bb.0: # %entry
; LINUX-64-STATIC-NEXT: movl lsrc+{{.*}}(%rip), %eax
@@ -1938,7 +1916,7 @@ entry:
ret void
}
-define void @qux07() nounwind {
+define dso_local void @qux07() nounwind {
; LINUX-64-STATIC-LABEL: qux07:
; LINUX-64-STATIC: # %bb.0: # %entry
; LINUX-64-STATIC-NEXT: movq $ldst+64, {{.*}}(%rip)
@@ -2008,7 +1986,7 @@ entry:
ret void
}
-define void @qux08() nounwind {
+define dso_local void @qux08() nounwind {
; LINUX-64-STATIC-LABEL: qux08:
; LINUX-64-STATIC: # %bb.0: # %entry
; LINUX-64-STATIC-NEXT: movl lsrc+{{.*}}(%rip), %eax
@@ -2095,7 +2073,7 @@ entry:
ret void
}
-define void @ind00(i64 %i) nounwind {
+define dso_local void @ind00(i64 %i) nounwind {
; LINUX-64-STATIC-LABEL: ind00:
; LINUX-64-STATIC: # %bb.0: # %entry
; LINUX-64-STATIC-NEXT: movq src@{{.*}}(%rip), %rax
@@ -2193,7 +2171,7 @@ entry:
ret void
}
-define void @ixd00(i64 %i) nounwind {
+define dso_local void @ixd00(i64 %i) nounwind {
; LINUX-64-STATIC-LABEL: ixd00:
; LINUX-64-STATIC: # %bb.0: # %entry
; LINUX-64-STATIC-NEXT: movq xsrc@{{.*}}(%rip), %rax
@@ -2291,7 +2269,7 @@ entry:
ret void
}
-define void @ind01(i64 %i) nounwind {
+define dso_local void @ind01(i64 %i) nounwind {
; LINUX-64-STATIC-LABEL: ind01:
; LINUX-64-STATIC: # %bb.0: # %entry
; LINUX-64-STATIC-NEXT: shlq $2, %rdi
@@ -2387,7 +2365,7 @@ entry:
ret void
}
-define void @ixd01(i64 %i) nounwind {
+define dso_local void @ixd01(i64 %i) nounwind {
; LINUX-64-STATIC-LABEL: ixd01:
; LINUX-64-STATIC: # %bb.0: # %entry
; LINUX-64-STATIC-NEXT: shlq $2, %rdi
@@ -2483,7 +2461,7 @@ entry:
ret void
}
-define void @ind02(i64 %i) nounwind {
+define dso_local void @ind02(i64 %i) nounwind {
; LINUX-64-STATIC-LABEL: ind02:
; LINUX-64-STATIC: # %bb.0: # %entry
; LINUX-64-STATIC-NEXT: movq src@{{.*}}(%rip), %rax
@@ -2592,7 +2570,7 @@ entry:
ret void
}
-define void @ixd02(i64 %i) nounwind {
+define dso_local void @ixd02(i64 %i) nounwind {
; LINUX-64-STATIC-LABEL: ixd02:
; LINUX-64-STATIC: # %bb.0: # %entry
; LINUX-64-STATIC-NEXT: movq xsrc@{{.*}}(%rip), %rax
@@ -2701,7 +2679,7 @@ entry:
ret void
}
-define void @ind03(i64 %i) nounwind {
+define dso_local void @ind03(i64 %i) nounwind {
; LINUX-64-STATIC-LABEL: ind03:
; LINUX-64-STATIC: # %bb.0: # %entry
; LINUX-64-STATIC-NEXT: movl dsrc(,%rdi,4), %eax
@@ -2723,17 +2701,15 @@ define void @ind03(i64 %i) nounwind {
; LINUX-32-PIC-NEXT: .Ltmp30:
; LINUX-32-PIC-NEXT: addl $_GLOBAL_OFFSET_TABLE_+(.Ltmp30-.L30$pb), %eax
; LINUX-32-PIC-NEXT: movl {{[0-9]+}}(%esp), %ecx
-; LINUX-32-PIC-NEXT: movl dsrc at GOT(%eax), %edx
-; LINUX-32-PIC-NEXT: movl (%edx,%ecx,4), %edx
-; LINUX-32-PIC-NEXT: movl ddst at GOT(%eax), %eax
-; LINUX-32-PIC-NEXT: movl %edx, (%eax,%ecx,4)
+; LINUX-32-PIC-NEXT: movl .Ldsrc$local at GOTOFF(%eax,%ecx,4), %edx
+; LINUX-32-PIC-NEXT: movl %edx, .Lddst$local at GOTOFF(%eax,%ecx,4)
; LINUX-32-PIC-NEXT: retl
;
; LINUX-64-PIC-LABEL: ind03:
; LINUX-64-PIC: # %bb.0: # %entry
-; LINUX-64-PIC-NEXT: movq dsrc@{{.*}}(%rip), %rax
+; LINUX-64-PIC-NEXT: leaq .Ldsrc${{.*}}(%rip), %rax
; LINUX-64-PIC-NEXT: movl (%rax,%rdi,4), %eax
-; LINUX-64-PIC-NEXT: movq ddst@{{.*}}(%rip), %rcx
+; LINUX-64-PIC-NEXT: leaq .Lddst${{.*}}(%rip), %rcx
; LINUX-64-PIC-NEXT: movl %eax, (%rcx,%rdi,4)
; LINUX-64-PIC-NEXT: retq
;
@@ -2793,7 +2769,7 @@ entry:
ret void
}
-define void @ind04(i64 %i) nounwind {
+define dso_local void @ind04(i64 %i) nounwind {
; LINUX-64-STATIC-LABEL: ind04:
; LINUX-64-STATIC: # %bb.0: # %entry
; LINUX-64-STATIC-NEXT: leaq ddst(,%rdi,4), %rax
@@ -2815,18 +2791,15 @@ define void @ind04(i64 %i) nounwind {
; LINUX-32-PIC-NEXT: .Ltmp31:
; LINUX-32-PIC-NEXT: addl $_GLOBAL_OFFSET_TABLE_+(.Ltmp31-.L31$pb), %eax
; LINUX-32-PIC-NEXT: movl {{[0-9]+}}(%esp), %ecx
-; LINUX-32-PIC-NEXT: shll $2, %ecx
-; LINUX-32-PIC-NEXT: addl ddst at GOT(%eax), %ecx
-; LINUX-32-PIC-NEXT: movl dptr at GOT(%eax), %eax
-; LINUX-32-PIC-NEXT: movl %ecx, (%eax)
+; LINUX-32-PIC-NEXT: leal .Lddst$local at GOTOFF(%eax,%ecx,4), %ecx
+; LINUX-32-PIC-NEXT: movl %ecx, .Ldptr$local at GOTOFF(%eax)
; LINUX-32-PIC-NEXT: retl
;
; LINUX-64-PIC-LABEL: ind04:
; LINUX-64-PIC: # %bb.0: # %entry
-; LINUX-64-PIC-NEXT: shlq $2, %rdi
-; LINUX-64-PIC-NEXT: addq ddst@{{.*}}(%rip), %rdi
-; LINUX-64-PIC-NEXT: movq dptr@{{.*}}(%rip), %rax
-; LINUX-64-PIC-NEXT: movq %rdi, (%rax)
+; LINUX-64-PIC-NEXT: leaq .Lddst${{.*}}(%rip), %rax
+; LINUX-64-PIC-NEXT: leaq (%rax,%rdi,4), %rax
+; LINUX-64-PIC-NEXT: movq %rax, .Ldptr${{.*}}(%rip)
; LINUX-64-PIC-NEXT: retq
;
; DARWIN-32-STATIC-LABEL: ind04:
@@ -2880,7 +2853,7 @@ entry:
ret void
}
-define void @ind05(i64 %i) nounwind {
+define dso_local void @ind05(i64 %i) nounwind {
; LINUX-64-STATIC-LABEL: ind05:
; LINUX-64-STATIC: # %bb.0: # %entry
; LINUX-64-STATIC-NEXT: movl dsrc(,%rdi,4), %eax
@@ -2904,19 +2877,16 @@ define void @ind05(i64 %i) nounwind {
; LINUX-32-PIC-NEXT: .Ltmp32:
; LINUX-32-PIC-NEXT: addl $_GLOBAL_OFFSET_TABLE_+(.Ltmp32-.L32$pb), %eax
; LINUX-32-PIC-NEXT: movl {{[0-9]+}}(%esp), %ecx
-; LINUX-32-PIC-NEXT: movl dsrc at GOT(%eax), %edx
-; LINUX-32-PIC-NEXT: movl (%edx,%ecx,4), %edx
-; LINUX-32-PIC-NEXT: movl dptr at GOT(%eax), %eax
-; LINUX-32-PIC-NEXT: movl (%eax), %eax
+; LINUX-32-PIC-NEXT: movl .Ldsrc$local at GOTOFF(%eax,%ecx,4), %edx
+; LINUX-32-PIC-NEXT: movl .Ldptr$local at GOTOFF(%eax), %eax
; LINUX-32-PIC-NEXT: movl %edx, (%eax,%ecx,4)
; LINUX-32-PIC-NEXT: retl
;
; LINUX-64-PIC-LABEL: ind05:
; LINUX-64-PIC: # %bb.0: # %entry
-; LINUX-64-PIC-NEXT: movq dsrc@{{.*}}(%rip), %rax
+; LINUX-64-PIC-NEXT: leaq .Ldsrc${{.*}}(%rip), %rax
; LINUX-64-PIC-NEXT: movl (%rax,%rdi,4), %eax
-; LINUX-64-PIC-NEXT: movq dptr@{{.*}}(%rip), %rcx
-; LINUX-64-PIC-NEXT: movq (%rcx), %rcx
+; LINUX-64-PIC-NEXT: movq .Ldptr${{.*}}(%rip), %rcx
; LINUX-64-PIC-NEXT: movl %eax, (%rcx,%rdi,4)
; LINUX-64-PIC-NEXT: retq
;
@@ -2980,7 +2950,7 @@ entry:
ret void
}
-define void @ind06(i64 %i) nounwind {
+define dso_local void @ind06(i64 %i) nounwind {
; LINUX-64-STATIC-LABEL: ind06:
; LINUX-64-STATIC: # %bb.0: # %entry
; LINUX-64-STATIC-NEXT: movl lsrc(,%rdi,4), %eax
@@ -3070,7 +3040,7 @@ entry:
ret void
}
-define void @ind07(i64 %i) nounwind {
+define dso_local void @ind07(i64 %i) nounwind {
; LINUX-64-STATIC-LABEL: ind07:
; LINUX-64-STATIC: # %bb.0: # %entry
; LINUX-64-STATIC-NEXT: leaq ldst(,%rdi,4), %rax
@@ -3154,7 +3124,7 @@ entry:
ret void
}
-define void @ind08(i64 %i) nounwind {
+define dso_local void @ind08(i64 %i) nounwind {
; LINUX-64-STATIC-LABEL: ind08:
; LINUX-64-STATIC: # %bb.0: # %entry
; LINUX-64-STATIC-NEXT: movl lsrc(,%rdi,4), %eax
@@ -3251,7 +3221,7 @@ entry:
ret void
}
-define void @off00(i64 %i) nounwind {
+define dso_local void @off00(i64 %i) nounwind {
; LINUX-64-STATIC-LABEL: off00:
; LINUX-64-STATIC: # %bb.0: # %entry
; LINUX-64-STATIC-NEXT: movq src@{{.*}}(%rip), %rax
@@ -3350,7 +3320,7 @@ entry:
ret void
}
-define void @oxf00(i64 %i) nounwind {
+define dso_local void @oxf00(i64 %i) nounwind {
; LINUX-64-STATIC-LABEL: oxf00:
; LINUX-64-STATIC: # %bb.0: # %entry
; LINUX-64-STATIC-NEXT: movq xsrc@{{.*}}(%rip), %rax
@@ -3449,7 +3419,7 @@ entry:
ret void
}
-define void @off01(i64 %i) nounwind {
+define dso_local void @off01(i64 %i) nounwind {
; LINUX-64-STATIC-LABEL: off01:
; LINUX-64-STATIC: # %bb.0: # %entry
; LINUX-64-STATIC-NEXT: movq dst@{{.*}}(%rip), %rax
@@ -3546,7 +3516,7 @@ entry:
ret void
}
-define void @oxf01(i64 %i) nounwind {
+define dso_local void @oxf01(i64 %i) nounwind {
; LINUX-64-STATIC-LABEL: oxf01:
; LINUX-64-STATIC: # %bb.0: # %entry
; LINUX-64-STATIC-NEXT: movq xdst@{{.*}}(%rip), %rax
@@ -3643,7 +3613,7 @@ entry:
ret void
}
-define void @off02(i64 %i) nounwind {
+define dso_local void @off02(i64 %i) nounwind {
; LINUX-64-STATIC-LABEL: off02:
; LINUX-64-STATIC: # %bb.0: # %entry
; LINUX-64-STATIC-NEXT: movq src@{{.*}}(%rip), %rax
@@ -3753,7 +3723,7 @@ entry:
ret void
}
-define void @oxf02(i64 %i) nounwind {
+define dso_local void @oxf02(i64 %i) nounwind {
; LINUX-64-STATIC-LABEL: oxf02:
; LINUX-64-STATIC: # %bb.0: # %entry
; LINUX-64-STATIC-NEXT: movq xsrc@{{.*}}(%rip), %rax
@@ -3863,7 +3833,7 @@ entry:
ret void
}
-define void @off03(i64 %i) nounwind {
+define dso_local void @off03(i64 %i) nounwind {
; LINUX-64-STATIC-LABEL: off03:
; LINUX-64-STATIC: # %bb.0: # %entry
; LINUX-64-STATIC-NEXT: movl dsrc+64(,%rdi,4), %eax
@@ -3885,17 +3855,15 @@ define void @off03(i64 %i) nounwind {
; LINUX-32-PIC-NEXT: .Ltmp42:
; LINUX-32-PIC-NEXT: addl $_GLOBAL_OFFSET_TABLE_+(.Ltmp42-.L42$pb), %eax
; LINUX-32-PIC-NEXT: movl {{[0-9]+}}(%esp), %ecx
-; LINUX-32-PIC-NEXT: movl dsrc at GOT(%eax), %edx
-; LINUX-32-PIC-NEXT: movl 64(%edx,%ecx,4), %edx
-; LINUX-32-PIC-NEXT: movl ddst at GOT(%eax), %eax
-; LINUX-32-PIC-NEXT: movl %edx, 64(%eax,%ecx,4)
+; LINUX-32-PIC-NEXT: movl .Ldsrc$local at GOTOFF+64(%eax,%ecx,4), %edx
+; LINUX-32-PIC-NEXT: movl %edx, .Lddst$local at GOTOFF+64(%eax,%ecx,4)
; LINUX-32-PIC-NEXT: retl
;
; LINUX-64-PIC-LABEL: off03:
; LINUX-64-PIC: # %bb.0: # %entry
-; LINUX-64-PIC-NEXT: movq dsrc@{{.*}}(%rip), %rax
+; LINUX-64-PIC-NEXT: leaq .Ldsrc${{.*}}(%rip), %rax
; LINUX-64-PIC-NEXT: movl 64(%rax,%rdi,4), %eax
-; LINUX-64-PIC-NEXT: movq ddst@{{.*}}(%rip), %rcx
+; LINUX-64-PIC-NEXT: leaq .Lddst${{.*}}(%rip), %rcx
; LINUX-64-PIC-NEXT: movl %eax, 64(%rcx,%rdi,4)
; LINUX-64-PIC-NEXT: retq
;
@@ -3956,7 +3924,7 @@ entry:
ret void
}
-define void @off04(i64 %i) nounwind {
+define dso_local void @off04(i64 %i) nounwind {
; LINUX-64-STATIC-LABEL: off04:
; LINUX-64-STATIC: # %bb.0: # %entry
; LINUX-64-STATIC-NEXT: leaq ddst+64(,%rdi,4), %rax
@@ -3978,18 +3946,15 @@ define void @off04(i64 %i) nounwind {
; LINUX-32-PIC-NEXT: .Ltmp43:
; LINUX-32-PIC-NEXT: addl $_GLOBAL_OFFSET_TABLE_+(.Ltmp43-.L43$pb), %eax
; LINUX-32-PIC-NEXT: movl {{[0-9]+}}(%esp), %ecx
-; LINUX-32-PIC-NEXT: movl ddst at GOT(%eax), %edx
-; LINUX-32-PIC-NEXT: leal 64(%edx,%ecx,4), %ecx
-; LINUX-32-PIC-NEXT: movl dptr at GOT(%eax), %eax
-; LINUX-32-PIC-NEXT: movl %ecx, (%eax)
+; LINUX-32-PIC-NEXT: leal .Lddst$local at GOTOFF+64(%eax,%ecx,4), %ecx
+; LINUX-32-PIC-NEXT: movl %ecx, .Ldptr$local at GOTOFF(%eax)
; LINUX-32-PIC-NEXT: retl
;
; LINUX-64-PIC-LABEL: off04:
; LINUX-64-PIC: # %bb.0: # %entry
-; LINUX-64-PIC-NEXT: movq ddst@{{.*}}(%rip), %rax
+; LINUX-64-PIC-NEXT: leaq .Lddst${{.*}}(%rip), %rax
; LINUX-64-PIC-NEXT: leaq 64(%rax,%rdi,4), %rax
-; LINUX-64-PIC-NEXT: movq dptr@{{.*}}(%rip), %rcx
-; LINUX-64-PIC-NEXT: movq %rax, (%rcx)
+; LINUX-64-PIC-NEXT: movq %rax, .Ldptr${{.*}}(%rip)
; LINUX-64-PIC-NEXT: retq
;
; DARWIN-32-STATIC-LABEL: off04:
@@ -4044,7 +4009,7 @@ entry:
ret void
}
-define void @off05(i64 %i) nounwind {
+define dso_local void @off05(i64 %i) nounwind {
; LINUX-64-STATIC-LABEL: off05:
; LINUX-64-STATIC: # %bb.0: # %entry
; LINUX-64-STATIC-NEXT: movl dsrc+64(,%rdi,4), %eax
@@ -4068,19 +4033,16 @@ define void @off05(i64 %i) nounwind {
; LINUX-32-PIC-NEXT: .Ltmp44:
; LINUX-32-PIC-NEXT: addl $_GLOBAL_OFFSET_TABLE_+(.Ltmp44-.L44$pb), %eax
; LINUX-32-PIC-NEXT: movl {{[0-9]+}}(%esp), %ecx
-; LINUX-32-PIC-NEXT: movl dsrc at GOT(%eax), %edx
-; LINUX-32-PIC-NEXT: movl 64(%edx,%ecx,4), %edx
-; LINUX-32-PIC-NEXT: movl dptr at GOT(%eax), %eax
-; LINUX-32-PIC-NEXT: movl (%eax), %eax
+; LINUX-32-PIC-NEXT: movl .Ldsrc$local at GOTOFF+64(%eax,%ecx,4), %edx
+; LINUX-32-PIC-NEXT: movl .Ldptr$local at GOTOFF(%eax), %eax
; LINUX-32-PIC-NEXT: movl %edx, 64(%eax,%ecx,4)
; LINUX-32-PIC-NEXT: retl
;
; LINUX-64-PIC-LABEL: off05:
; LINUX-64-PIC: # %bb.0: # %entry
-; LINUX-64-PIC-NEXT: movq dsrc@{{.*}}(%rip), %rax
+; LINUX-64-PIC-NEXT: leaq .Ldsrc${{.*}}(%rip), %rax
; LINUX-64-PIC-NEXT: movl 64(%rax,%rdi,4), %eax
-; LINUX-64-PIC-NEXT: movq dptr@{{.*}}(%rip), %rcx
-; LINUX-64-PIC-NEXT: movq (%rcx), %rcx
+; LINUX-64-PIC-NEXT: movq .Ldptr${{.*}}(%rip), %rcx
; LINUX-64-PIC-NEXT: movl %eax, 64(%rcx,%rdi,4)
; LINUX-64-PIC-NEXT: retq
;
@@ -4145,7 +4107,7 @@ entry:
ret void
}
-define void @off06(i64 %i) nounwind {
+define dso_local void @off06(i64 %i) nounwind {
; LINUX-64-STATIC-LABEL: off06:
; LINUX-64-STATIC: # %bb.0: # %entry
; LINUX-64-STATIC-NEXT: movl lsrc+64(,%rdi,4), %eax
@@ -4236,7 +4198,7 @@ entry:
ret void
}
-define void @off07(i64 %i) nounwind {
+define dso_local void @off07(i64 %i) nounwind {
; LINUX-64-STATIC-LABEL: off07:
; LINUX-64-STATIC: # %bb.0: # %entry
; LINUX-64-STATIC-NEXT: leaq ldst+64(,%rdi,4), %rax
@@ -4321,7 +4283,7 @@ entry:
ret void
}
-define void @off08(i64 %i) nounwind {
+define dso_local void @off08(i64 %i) nounwind {
; LINUX-64-STATIC-LABEL: off08:
; LINUX-64-STATIC: # %bb.0: # %entry
; LINUX-64-STATIC-NEXT: movl lsrc+64(,%rdi,4), %eax
@@ -4419,7 +4381,7 @@ entry:
ret void
}
-define void @moo00(i64 %i) nounwind {
+define dso_local void @moo00(i64 %i) nounwind {
; LINUX-64-STATIC-LABEL: moo00:
; LINUX-64-STATIC: # %bb.0: # %entry
; LINUX-64-STATIC-NEXT: movq src@{{.*}}(%rip), %rax
@@ -4510,7 +4472,7 @@ entry:
ret void
}
-define void @moo01(i64 %i) nounwind {
+define dso_local void @moo01(i64 %i) nounwind {
; LINUX-64-STATIC-LABEL: moo01:
; LINUX-64-STATIC: # %bb.0: # %entry
; LINUX-64-STATIC-NEXT: movl $262144, %eax # imm = 0x40000
@@ -4599,7 +4561,7 @@ entry:
ret void
}
-define void @moo02(i64 %i) nounwind {
+define dso_local void @moo02(i64 %i) nounwind {
; LINUX-64-STATIC-LABEL: moo02:
; LINUX-64-STATIC: # %bb.0: # %entry
; LINUX-64-STATIC-NEXT: movq src@{{.*}}(%rip), %rax
@@ -4702,7 +4664,7 @@ entry:
ret void
}
-define void @moo03(i64 %i) nounwind {
+define dso_local void @moo03(i64 %i) nounwind {
; LINUX-64-STATIC-LABEL: moo03:
; LINUX-64-STATIC: # %bb.0: # %entry
; LINUX-64-STATIC-NEXT: movl dsrc+{{.*}}(%rip), %eax
@@ -4722,18 +4684,14 @@ define void @moo03(i64 %i) nounwind {
; LINUX-32-PIC-NEXT: popl %eax
; LINUX-32-PIC-NEXT: .Ltmp51:
; LINUX-32-PIC-NEXT: addl $_GLOBAL_OFFSET_TABLE_+(.Ltmp51-.L51$pb), %eax
-; LINUX-32-PIC-NEXT: movl dsrc at GOT(%eax), %ecx
-; LINUX-32-PIC-NEXT: movl 262144(%ecx), %ecx
-; LINUX-32-PIC-NEXT: movl ddst at GOT(%eax), %eax
-; LINUX-32-PIC-NEXT: movl %ecx, 262144(%eax)
+; LINUX-32-PIC-NEXT: movl .Ldsrc$local at GOTOFF+262144(%eax), %ecx
+; LINUX-32-PIC-NEXT: movl %ecx, .Lddst$local at GOTOFF+262144(%eax)
; LINUX-32-PIC-NEXT: retl
;
; LINUX-64-PIC-LABEL: moo03:
; LINUX-64-PIC: # %bb.0: # %entry
-; LINUX-64-PIC-NEXT: movq dsrc@{{.*}}(%rip), %rax
-; LINUX-64-PIC-NEXT: movl 262144(%rax), %eax
-; LINUX-64-PIC-NEXT: movq ddst@{{.*}}(%rip), %rcx
-; LINUX-64-PIC-NEXT: movl %eax, 262144(%rcx)
+; LINUX-64-PIC-NEXT: movl .Ldsrc$local+{{.*}}(%rip), %eax
+; LINUX-64-PIC-NEXT: movl %eax, .Lddst$local+{{.*}}(%rip)
; LINUX-64-PIC-NEXT: retq
;
; DARWIN-32-STATIC-LABEL: moo03:
@@ -4781,7 +4739,7 @@ entry:
ret void
}
-define void @moo04(i64 %i) nounwind {
+define dso_local void @moo04(i64 %i) nounwind {
; LINUX-64-STATIC-LABEL: moo04:
; LINUX-64-STATIC: # %bb.0: # %entry
; LINUX-64-STATIC-NEXT: movq $ddst+262144, {{.*}}(%rip)
@@ -4799,18 +4757,14 @@ define void @moo04(i64 %i) nounwind {
; LINUX-32-PIC-NEXT: popl %eax
; LINUX-32-PIC-NEXT: .Ltmp52:
; LINUX-32-PIC-NEXT: addl $_GLOBAL_OFFSET_TABLE_+(.Ltmp52-.L52$pb), %eax
-; LINUX-32-PIC-NEXT: movl $262144, %ecx # imm = 0x40000
-; LINUX-32-PIC-NEXT: addl ddst at GOT(%eax), %ecx
-; LINUX-32-PIC-NEXT: movl dptr at GOT(%eax), %eax
-; LINUX-32-PIC-NEXT: movl %ecx, (%eax)
+; LINUX-32-PIC-NEXT: leal .Lddst$local at GOTOFF+262144(%eax), %ecx
+; LINUX-32-PIC-NEXT: movl %ecx, .Ldptr$local at GOTOFF(%eax)
; LINUX-32-PIC-NEXT: retl
;
; LINUX-64-PIC-LABEL: moo04:
; LINUX-64-PIC: # %bb.0: # %entry
-; LINUX-64-PIC-NEXT: movl $262144, %eax # imm = 0x40000
-; LINUX-64-PIC-NEXT: addq ddst@{{.*}}(%rip), %rax
-; LINUX-64-PIC-NEXT: movq dptr@{{.*}}(%rip), %rcx
-; LINUX-64-PIC-NEXT: movq %rax, (%rcx)
+; LINUX-64-PIC-NEXT: leaq .Lddst$local+{{.*}}(%rip), %rax
+; LINUX-64-PIC-NEXT: movq %rax, .Ldptr${{.*}}(%rip)
; LINUX-64-PIC-NEXT: retq
;
; DARWIN-32-STATIC-LABEL: moo04:
@@ -4855,7 +4809,7 @@ entry:
ret void
}
-define void @moo05(i64 %i) nounwind {
+define dso_local void @moo05(i64 %i) nounwind {
; LINUX-64-STATIC-LABEL: moo05:
; LINUX-64-STATIC: # %bb.0: # %entry
; LINUX-64-STATIC-NEXT: movl dsrc+{{.*}}(%rip), %eax
@@ -4877,19 +4831,15 @@ define void @moo05(i64 %i) nounwind {
; LINUX-32-PIC-NEXT: popl %eax
; LINUX-32-PIC-NEXT: .Ltmp53:
; LINUX-32-PIC-NEXT: addl $_GLOBAL_OFFSET_TABLE_+(.Ltmp53-.L53$pb), %eax
-; LINUX-32-PIC-NEXT: movl dsrc at GOT(%eax), %ecx
-; LINUX-32-PIC-NEXT: movl 262144(%ecx), %ecx
-; LINUX-32-PIC-NEXT: movl dptr at GOT(%eax), %eax
-; LINUX-32-PIC-NEXT: movl (%eax), %eax
+; LINUX-32-PIC-NEXT: movl .Ldsrc$local at GOTOFF+262144(%eax), %ecx
+; LINUX-32-PIC-NEXT: movl .Ldptr$local at GOTOFF(%eax), %eax
; LINUX-32-PIC-NEXT: movl %ecx, 262144(%eax)
; LINUX-32-PIC-NEXT: retl
;
; LINUX-64-PIC-LABEL: moo05:
; LINUX-64-PIC: # %bb.0: # %entry
-; LINUX-64-PIC-NEXT: movq dsrc@{{.*}}(%rip), %rax
-; LINUX-64-PIC-NEXT: movl 262144(%rax), %eax
-; LINUX-64-PIC-NEXT: movq dptr@{{.*}}(%rip), %rcx
-; LINUX-64-PIC-NEXT: movq (%rcx), %rcx
+; LINUX-64-PIC-NEXT: movl .Ldsrc$local+{{.*}}(%rip), %eax
+; LINUX-64-PIC-NEXT: movq .Ldptr${{.*}}(%rip), %rcx
; LINUX-64-PIC-NEXT: movl %eax, 262144(%rcx)
; LINUX-64-PIC-NEXT: retq
;
@@ -4946,7 +4896,7 @@ entry:
ret void
}
-define void @moo06(i64 %i) nounwind {
+define dso_local void @moo06(i64 %i) nounwind {
; LINUX-64-STATIC-LABEL: moo06:
; LINUX-64-STATIC: # %bb.0: # %entry
; LINUX-64-STATIC-NEXT: movl lsrc+{{.*}}(%rip), %eax
@@ -5021,7 +4971,7 @@ entry:
ret void
}
-define void @moo07(i64 %i) nounwind {
+define dso_local void @moo07(i64 %i) nounwind {
; LINUX-64-STATIC-LABEL: moo07:
; LINUX-64-STATIC: # %bb.0: # %entry
; LINUX-64-STATIC-NEXT: movq $ldst+262144, {{.*}}(%rip)
@@ -5091,7 +5041,7 @@ entry:
ret void
}
-define void @moo08(i64 %i) nounwind {
+define dso_local void @moo08(i64 %i) nounwind {
; LINUX-64-STATIC-LABEL: moo08:
; LINUX-64-STATIC: # %bb.0: # %entry
; LINUX-64-STATIC-NEXT: movl lsrc+{{.*}}(%rip), %eax
@@ -5178,7 +5128,7 @@ entry:
ret void
}
-define void @big00(i64 %i) nounwind {
+define dso_local void @big00(i64 %i) nounwind {
; LINUX-64-STATIC-LABEL: big00:
; LINUX-64-STATIC: # %bb.0: # %entry
; LINUX-64-STATIC-NEXT: movq src@{{.*}}(%rip), %rax
@@ -5277,7 +5227,7 @@ entry:
ret void
}
-define void @big01(i64 %i) nounwind {
+define dso_local void @big01(i64 %i) nounwind {
; LINUX-64-STATIC-LABEL: big01:
; LINUX-64-STATIC: # %bb.0: # %entry
; LINUX-64-STATIC-NEXT: movq dst@{{.*}}(%rip), %rax
@@ -5374,7 +5324,7 @@ entry:
ret void
}
-define void @big02(i64 %i) nounwind {
+define dso_local void @big02(i64 %i) nounwind {
; LINUX-64-STATIC-LABEL: big02:
; LINUX-64-STATIC: # %bb.0: # %entry
; LINUX-64-STATIC-NEXT: movq src@{{.*}}(%rip), %rax
@@ -5484,7 +5434,7 @@ entry:
ret void
}
-define void @big03(i64 %i) nounwind {
+define dso_local void @big03(i64 %i) nounwind {
; LINUX-64-STATIC-LABEL: big03:
; LINUX-64-STATIC: # %bb.0: # %entry
; LINUX-64-STATIC-NEXT: movl dsrc+262144(,%rdi,4), %eax
@@ -5506,17 +5456,15 @@ define void @big03(i64 %i) nounwind {
; LINUX-32-PIC-NEXT: .Ltmp60:
; LINUX-32-PIC-NEXT: addl $_GLOBAL_OFFSET_TABLE_+(.Ltmp60-.L60$pb), %eax
; LINUX-32-PIC-NEXT: movl {{[0-9]+}}(%esp), %ecx
-; LINUX-32-PIC-NEXT: movl dsrc at GOT(%eax), %edx
-; LINUX-32-PIC-NEXT: movl 262144(%edx,%ecx,4), %edx
-; LINUX-32-PIC-NEXT: movl ddst at GOT(%eax), %eax
-; LINUX-32-PIC-NEXT: movl %edx, 262144(%eax,%ecx,4)
+; LINUX-32-PIC-NEXT: movl .Ldsrc$local at GOTOFF+262144(%eax,%ecx,4), %edx
+; LINUX-32-PIC-NEXT: movl %edx, .Lddst$local at GOTOFF+262144(%eax,%ecx,4)
; LINUX-32-PIC-NEXT: retl
;
; LINUX-64-PIC-LABEL: big03:
; LINUX-64-PIC: # %bb.0: # %entry
-; LINUX-64-PIC-NEXT: movq dsrc@{{.*}}(%rip), %rax
+; LINUX-64-PIC-NEXT: leaq .Ldsrc${{.*}}(%rip), %rax
; LINUX-64-PIC-NEXT: movl 262144(%rax,%rdi,4), %eax
-; LINUX-64-PIC-NEXT: movq ddst@{{.*}}(%rip), %rcx
+; LINUX-64-PIC-NEXT: leaq .Lddst${{.*}}(%rip), %rcx
; LINUX-64-PIC-NEXT: movl %eax, 262144(%rcx,%rdi,4)
; LINUX-64-PIC-NEXT: retq
;
@@ -5577,7 +5525,7 @@ entry:
ret void
}
-define void @big04(i64 %i) nounwind {
+define dso_local void @big04(i64 %i) nounwind {
; LINUX-64-STATIC-LABEL: big04:
; LINUX-64-STATIC: # %bb.0: # %entry
; LINUX-64-STATIC-NEXT: leaq ddst+262144(,%rdi,4), %rax
@@ -5599,18 +5547,15 @@ define void @big04(i64 %i) nounwind {
; LINUX-32-PIC-NEXT: .Ltmp61:
; LINUX-32-PIC-NEXT: addl $_GLOBAL_OFFSET_TABLE_+(.Ltmp61-.L61$pb), %eax
; LINUX-32-PIC-NEXT: movl {{[0-9]+}}(%esp), %ecx
-; LINUX-32-PIC-NEXT: movl ddst at GOT(%eax), %edx
-; LINUX-32-PIC-NEXT: leal 262144(%edx,%ecx,4), %ecx
-; LINUX-32-PIC-NEXT: movl dptr at GOT(%eax), %eax
-; LINUX-32-PIC-NEXT: movl %ecx, (%eax)
+; LINUX-32-PIC-NEXT: leal .Lddst$local at GOTOFF+262144(%eax,%ecx,4), %ecx
+; LINUX-32-PIC-NEXT: movl %ecx, .Ldptr$local at GOTOFF(%eax)
; LINUX-32-PIC-NEXT: retl
;
; LINUX-64-PIC-LABEL: big04:
; LINUX-64-PIC: # %bb.0: # %entry
-; LINUX-64-PIC-NEXT: movq ddst@{{.*}}(%rip), %rax
+; LINUX-64-PIC-NEXT: leaq .Lddst${{.*}}(%rip), %rax
; LINUX-64-PIC-NEXT: leaq 262144(%rax,%rdi,4), %rax
-; LINUX-64-PIC-NEXT: movq dptr@{{.*}}(%rip), %rcx
-; LINUX-64-PIC-NEXT: movq %rax, (%rcx)
+; LINUX-64-PIC-NEXT: movq %rax, .Ldptr${{.*}}(%rip)
; LINUX-64-PIC-NEXT: retq
;
; DARWIN-32-STATIC-LABEL: big04:
@@ -5665,7 +5610,7 @@ entry:
ret void
}
-define void @big05(i64 %i) nounwind {
+define dso_local void @big05(i64 %i) nounwind {
; LINUX-64-STATIC-LABEL: big05:
; LINUX-64-STATIC: # %bb.0: # %entry
; LINUX-64-STATIC-NEXT: movl dsrc+262144(,%rdi,4), %eax
@@ -5689,19 +5634,16 @@ define void @big05(i64 %i) nounwind {
; LINUX-32-PIC-NEXT: .Ltmp62:
; LINUX-32-PIC-NEXT: addl $_GLOBAL_OFFSET_TABLE_+(.Ltmp62-.L62$pb), %eax
; LINUX-32-PIC-NEXT: movl {{[0-9]+}}(%esp), %ecx
-; LINUX-32-PIC-NEXT: movl dsrc at GOT(%eax), %edx
-; LINUX-32-PIC-NEXT: movl 262144(%edx,%ecx,4), %edx
-; LINUX-32-PIC-NEXT: movl dptr at GOT(%eax), %eax
-; LINUX-32-PIC-NEXT: movl (%eax), %eax
+; LINUX-32-PIC-NEXT: movl .Ldsrc$local at GOTOFF+262144(%eax,%ecx,4), %edx
+; LINUX-32-PIC-NEXT: movl .Ldptr$local at GOTOFF(%eax), %eax
; LINUX-32-PIC-NEXT: movl %edx, 262144(%eax,%ecx,4)
; LINUX-32-PIC-NEXT: retl
;
; LINUX-64-PIC-LABEL: big05:
; LINUX-64-PIC: # %bb.0: # %entry
-; LINUX-64-PIC-NEXT: movq dsrc@{{.*}}(%rip), %rax
+; LINUX-64-PIC-NEXT: leaq .Ldsrc${{.*}}(%rip), %rax
; LINUX-64-PIC-NEXT: movl 262144(%rax,%rdi,4), %eax
-; LINUX-64-PIC-NEXT: movq dptr@{{.*}}(%rip), %rcx
-; LINUX-64-PIC-NEXT: movq (%rcx), %rcx
+; LINUX-64-PIC-NEXT: movq .Ldptr${{.*}}(%rip), %rcx
; LINUX-64-PIC-NEXT: movl %eax, 262144(%rcx,%rdi,4)
; LINUX-64-PIC-NEXT: retq
;
@@ -5766,7 +5708,7 @@ entry:
ret void
}
-define void @big06(i64 %i) nounwind {
+define dso_local void @big06(i64 %i) nounwind {
; LINUX-64-STATIC-LABEL: big06:
; LINUX-64-STATIC: # %bb.0: # %entry
; LINUX-64-STATIC-NEXT: movl lsrc+262144(,%rdi,4), %eax
@@ -5857,7 +5799,7 @@ entry:
ret void
}
-define void @big07(i64 %i) nounwind {
+define dso_local void @big07(i64 %i) nounwind {
; LINUX-64-STATIC-LABEL: big07:
; LINUX-64-STATIC: # %bb.0: # %entry
; LINUX-64-STATIC-NEXT: leaq ldst+262144(,%rdi,4), %rax
@@ -5942,7 +5884,7 @@ entry:
ret void
}
-define void @big08(i64 %i) nounwind {
+define dso_local void @big08(i64 %i) nounwind {
; LINUX-64-STATIC-LABEL: big08:
; LINUX-64-STATIC: # %bb.0: # %entry
; LINUX-64-STATIC-NEXT: movl lsrc+262144(,%rdi,4), %eax
@@ -6040,7 +5982,7 @@ entry:
ret void
}
-define i8* @bar00() nounwind {
+define dso_local i8* @bar00() nounwind {
; LINUX-64-STATIC-LABEL: bar00:
; LINUX-64-STATIC: # %bb.0: # %entry
; LINUX-64-STATIC-NEXT: movq src@{{.*}}(%rip), %rax
@@ -6103,7 +6045,7 @@ entry:
ret i8* bitcast ([131072 x i32]* @src to i8*)
}
-define i8* @bxr00() nounwind {
+define dso_local i8* @bxr00() nounwind {
; LINUX-64-STATIC-LABEL: bxr00:
; LINUX-64-STATIC: # %bb.0: # %entry
; LINUX-64-STATIC-NEXT: movq xsrc@{{.*}}(%rip), %rax
@@ -6166,7 +6108,7 @@ entry:
ret i8* bitcast ([32 x i32]* @xsrc to i8*)
}
-define i8* @bar01() nounwind {
+define dso_local i8* @bar01() nounwind {
; LINUX-64-STATIC-LABEL: bar01:
; LINUX-64-STATIC: # %bb.0: # %entry
; LINUX-64-STATIC-NEXT: movq dst@{{.*}}(%rip), %rax
@@ -6229,7 +6171,7 @@ entry:
ret i8* bitcast ([131072 x i32]* @dst to i8*)
}
-define i8* @bxr01() nounwind {
+define dso_local i8* @bxr01() nounwind {
; LINUX-64-STATIC-LABEL: bxr01:
; LINUX-64-STATIC: # %bb.0: # %entry
; LINUX-64-STATIC-NEXT: movq xdst@{{.*}}(%rip), %rax
@@ -6292,7 +6234,7 @@ entry:
ret i8* bitcast ([32 x i32]* @xdst to i8*)
}
-define i8* @bar02() nounwind {
+define dso_local i8* @bar02() nounwind {
; LINUX-64-STATIC-LABEL: bar02:
; LINUX-64-STATIC: # %bb.0: # %entry
; LINUX-64-STATIC-NEXT: movq ptr@{{.*}}(%rip), %rax
@@ -6355,7 +6297,7 @@ entry:
ret i8* bitcast (i32** @ptr to i8*)
}
-define i8* @bar03() nounwind {
+define dso_local i8* @bar03() nounwind {
; LINUX-64-STATIC-LABEL: bar03:
; LINUX-64-STATIC: # %bb.0: # %entry
; LINUX-64-STATIC-NEXT: movl $dsrc, %eax
@@ -6373,12 +6315,12 @@ define i8* @bar03() nounwind {
; LINUX-32-PIC-NEXT: popl %eax
; LINUX-32-PIC-NEXT: .Ltmp71:
; LINUX-32-PIC-NEXT: addl $_GLOBAL_OFFSET_TABLE_+(.Ltmp71-.L71$pb), %eax
-; LINUX-32-PIC-NEXT: movl dsrc at GOT(%eax), %eax
+; LINUX-32-PIC-NEXT: leal .Ldsrc$local at GOTOFF(%eax), %eax
; LINUX-32-PIC-NEXT: retl
;
; LINUX-64-PIC-LABEL: bar03:
; LINUX-64-PIC: # %bb.0: # %entry
-; LINUX-64-PIC-NEXT: movq dsrc@{{.*}}(%rip), %rax
+; LINUX-64-PIC-NEXT: leaq .Ldsrc${{.*}}(%rip), %rax
; LINUX-64-PIC-NEXT: retq
;
; DARWIN-32-STATIC-LABEL: bar03:
@@ -6418,7 +6360,7 @@ entry:
ret i8* bitcast ([131072 x i32]* @dsrc to i8*)
}
-define i8* @bar04() nounwind {
+define dso_local i8* @bar04() nounwind {
; LINUX-64-STATIC-LABEL: bar04:
; LINUX-64-STATIC: # %bb.0: # %entry
; LINUX-64-STATIC-NEXT: movl $ddst, %eax
@@ -6436,12 +6378,12 @@ define i8* @bar04() nounwind {
; LINUX-32-PIC-NEXT: popl %eax
; LINUX-32-PIC-NEXT: .Ltmp72:
; LINUX-32-PIC-NEXT: addl $_GLOBAL_OFFSET_TABLE_+(.Ltmp72-.L72$pb), %eax
-; LINUX-32-PIC-NEXT: movl ddst at GOT(%eax), %eax
+; LINUX-32-PIC-NEXT: leal .Lddst$local at GOTOFF(%eax), %eax
; LINUX-32-PIC-NEXT: retl
;
; LINUX-64-PIC-LABEL: bar04:
; LINUX-64-PIC: # %bb.0: # %entry
-; LINUX-64-PIC-NEXT: movq ddst@{{.*}}(%rip), %rax
+; LINUX-64-PIC-NEXT: leaq .Lddst${{.*}}(%rip), %rax
; LINUX-64-PIC-NEXT: retq
;
; DARWIN-32-STATIC-LABEL: bar04:
@@ -6481,7 +6423,7 @@ entry:
ret i8* bitcast ([131072 x i32]* @ddst to i8*)
}
-define i8* @bar05() nounwind {
+define dso_local i8* @bar05() nounwind {
; LINUX-64-STATIC-LABEL: bar05:
; LINUX-64-STATIC: # %bb.0: # %entry
; LINUX-64-STATIC-NEXT: movl $dptr, %eax
@@ -6499,12 +6441,12 @@ define i8* @bar05() nounwind {
; LINUX-32-PIC-NEXT: popl %eax
; LINUX-32-PIC-NEXT: .Ltmp73:
; LINUX-32-PIC-NEXT: addl $_GLOBAL_OFFSET_TABLE_+(.Ltmp73-.L73$pb), %eax
-; LINUX-32-PIC-NEXT: movl dptr at GOT(%eax), %eax
+; LINUX-32-PIC-NEXT: leal .Ldptr$local at GOTOFF(%eax), %eax
; LINUX-32-PIC-NEXT: retl
;
; LINUX-64-PIC-LABEL: bar05:
; LINUX-64-PIC: # %bb.0: # %entry
-; LINUX-64-PIC-NEXT: movq dptr@{{.*}}(%rip), %rax
+; LINUX-64-PIC-NEXT: leaq .Ldptr${{.*}}(%rip), %rax
; LINUX-64-PIC-NEXT: retq
;
; DARWIN-32-STATIC-LABEL: bar05:
@@ -6544,7 +6486,7 @@ entry:
ret i8* bitcast (i32** @dptr to i8*)
}
-define i8* @bar06() nounwind {
+define dso_local i8* @bar06() nounwind {
; LINUX-64-STATIC-LABEL: bar06:
; LINUX-64-STATIC: # %bb.0: # %entry
; LINUX-64-STATIC-NEXT: movl $lsrc, %eax
@@ -6607,7 +6549,7 @@ entry:
ret i8* bitcast ([131072 x i32]* @lsrc to i8*)
}
-define i8* @bar07() nounwind {
+define dso_local i8* @bar07() nounwind {
; LINUX-64-STATIC-LABEL: bar07:
; LINUX-64-STATIC: # %bb.0: # %entry
; LINUX-64-STATIC-NEXT: movl $ldst, %eax
@@ -6670,7 +6612,7 @@ entry:
ret i8* bitcast ([131072 x i32]* @ldst to i8*)
}
-define i8* @bar08() nounwind {
+define dso_local i8* @bar08() nounwind {
; LINUX-64-STATIC-LABEL: bar08:
; LINUX-64-STATIC: # %bb.0: # %entry
; LINUX-64-STATIC-NEXT: movl $lptr, %eax
@@ -6733,7 +6675,7 @@ entry:
ret i8* bitcast (i32** @lptr to i8*)
}
-define i8* @har00() nounwind {
+define dso_local i8* @har00() nounwind {
; LINUX-64-STATIC-LABEL: har00:
; LINUX-64-STATIC: # %bb.0: # %entry
; LINUX-64-STATIC-NEXT: movq src@{{.*}}(%rip), %rax
@@ -6796,7 +6738,7 @@ entry:
ret i8* bitcast ([131072 x i32]* @src to i8*)
}
-define i8* @hxr00() nounwind {
+define dso_local i8* @hxr00() nounwind {
; LINUX-64-STATIC-LABEL: hxr00:
; LINUX-64-STATIC: # %bb.0: # %entry
; LINUX-64-STATIC-NEXT: movq xsrc@{{.*}}(%rip), %rax
@@ -6859,7 +6801,7 @@ entry:
ret i8* bitcast ([32 x i32]* @xsrc to i8*)
}
-define i8* @har01() nounwind {
+define dso_local i8* @har01() nounwind {
; LINUX-64-STATIC-LABEL: har01:
; LINUX-64-STATIC: # %bb.0: # %entry
; LINUX-64-STATIC-NEXT: movq dst@{{.*}}(%rip), %rax
@@ -6922,7 +6864,7 @@ entry:
ret i8* bitcast ([131072 x i32]* @dst to i8*)
}
-define i8* @hxr01() nounwind {
+define dso_local i8* @hxr01() nounwind {
; LINUX-64-STATIC-LABEL: hxr01:
; LINUX-64-STATIC: # %bb.0: # %entry
; LINUX-64-STATIC-NEXT: movq xdst@{{.*}}(%rip), %rax
@@ -6985,7 +6927,7 @@ entry:
ret i8* bitcast ([32 x i32]* @xdst to i8*)
}
-define i8* @har02() nounwind {
+define dso_local i8* @har02() nounwind {
; LINUX-64-STATIC-LABEL: har02:
; LINUX-64-STATIC: # %bb.0: # %entry
; LINUX-64-STATIC-NEXT: movq ptr@{{.*}}(%rip), %rax
@@ -7058,7 +7000,7 @@ entry:
ret i8* %1
}
-define i8* @har03() nounwind {
+define dso_local i8* @har03() nounwind {
; LINUX-64-STATIC-LABEL: har03:
; LINUX-64-STATIC: # %bb.0: # %entry
; LINUX-64-STATIC-NEXT: movl $dsrc, %eax
@@ -7076,12 +7018,12 @@ define i8* @har03() nounwind {
; LINUX-32-PIC-NEXT: popl %eax
; LINUX-32-PIC-NEXT: .Ltmp82:
; LINUX-32-PIC-NEXT: addl $_GLOBAL_OFFSET_TABLE_+(.Ltmp82-.L82$pb), %eax
-; LINUX-32-PIC-NEXT: movl dsrc at GOT(%eax), %eax
+; LINUX-32-PIC-NEXT: leal .Ldsrc$local at GOTOFF(%eax), %eax
; LINUX-32-PIC-NEXT: retl
;
; LINUX-64-PIC-LABEL: har03:
; LINUX-64-PIC: # %bb.0: # %entry
-; LINUX-64-PIC-NEXT: movq dsrc@{{.*}}(%rip), %rax
+; LINUX-64-PIC-NEXT: leaq .Ldsrc${{.*}}(%rip), %rax
; LINUX-64-PIC-NEXT: retq
;
; DARWIN-32-STATIC-LABEL: har03:
@@ -7121,7 +7063,7 @@ entry:
ret i8* bitcast ([131072 x i32]* @dsrc to i8*)
}
-define i8* @har04() nounwind {
+define dso_local i8* @har04() nounwind {
; LINUX-64-STATIC-LABEL: har04:
; LINUX-64-STATIC: # %bb.0: # %entry
; LINUX-64-STATIC-NEXT: movl $ddst, %eax
@@ -7139,12 +7081,12 @@ define i8* @har04() nounwind {
; LINUX-32-PIC-NEXT: popl %eax
; LINUX-32-PIC-NEXT: .Ltmp83:
; LINUX-32-PIC-NEXT: addl $_GLOBAL_OFFSET_TABLE_+(.Ltmp83-.L83$pb), %eax
-; LINUX-32-PIC-NEXT: movl ddst at GOT(%eax), %eax
+; LINUX-32-PIC-NEXT: leal .Lddst$local at GOTOFF(%eax), %eax
; LINUX-32-PIC-NEXT: retl
;
; LINUX-64-PIC-LABEL: har04:
; LINUX-64-PIC: # %bb.0: # %entry
-; LINUX-64-PIC-NEXT: movq ddst@{{.*}}(%rip), %rax
+; LINUX-64-PIC-NEXT: leaq .Lddst${{.*}}(%rip), %rax
; LINUX-64-PIC-NEXT: retq
;
; DARWIN-32-STATIC-LABEL: har04:
@@ -7184,7 +7126,7 @@ entry:
ret i8* bitcast ([131072 x i32]* @ddst to i8*)
}
-define i8* @har05() nounwind {
+define dso_local i8* @har05() nounwind {
; LINUX-64-STATIC-LABEL: har05:
; LINUX-64-STATIC: # %bb.0: # %entry
; LINUX-64-STATIC-NEXT: movq {{.*}}(%rip), %rax
@@ -7202,14 +7144,12 @@ define i8* @har05() nounwind {
; LINUX-32-PIC-NEXT: popl %eax
; LINUX-32-PIC-NEXT: .Ltmp84:
; LINUX-32-PIC-NEXT: addl $_GLOBAL_OFFSET_TABLE_+(.Ltmp84-.L84$pb), %eax
-; LINUX-32-PIC-NEXT: movl dptr at GOT(%eax), %eax
-; LINUX-32-PIC-NEXT: movl (%eax), %eax
+; LINUX-32-PIC-NEXT: movl .Ldptr$local at GOTOFF(%eax), %eax
; LINUX-32-PIC-NEXT: retl
;
; LINUX-64-PIC-LABEL: har05:
; LINUX-64-PIC: # %bb.0: # %entry
-; LINUX-64-PIC-NEXT: movq dptr@{{.*}}(%rip), %rax
-; LINUX-64-PIC-NEXT: movq (%rax), %rax
+; LINUX-64-PIC-NEXT: movq .Ldptr${{.*}}(%rip), %rax
; LINUX-64-PIC-NEXT: retq
;
; DARWIN-32-STATIC-LABEL: har05:
@@ -7251,7 +7191,7 @@ entry:
ret i8* %1
}
-define i8* @har06() nounwind {
+define dso_local i8* @har06() nounwind {
; LINUX-64-STATIC-LABEL: har06:
; LINUX-64-STATIC: # %bb.0: # %entry
; LINUX-64-STATIC-NEXT: movl $lsrc, %eax
@@ -7314,7 +7254,7 @@ entry:
ret i8* bitcast ([131072 x i32]* @lsrc to i8*)
}
-define i8* @har07() nounwind {
+define dso_local i8* @har07() nounwind {
; LINUX-64-STATIC-LABEL: har07:
; LINUX-64-STATIC: # %bb.0: # %entry
; LINUX-64-STATIC-NEXT: movl $ldst, %eax
@@ -7377,7 +7317,7 @@ entry:
ret i8* bitcast ([131072 x i32]* @ldst to i8*)
}
-define i8* @har08() nounwind {
+define dso_local i8* @har08() nounwind {
; LINUX-64-STATIC-LABEL: har08:
; LINUX-64-STATIC: # %bb.0: # %entry
; LINUX-64-STATIC-NEXT: movq {{.*}}(%rip), %rax
@@ -7442,7 +7382,7 @@ entry:
ret i8* %1
}
-define i8* @bat00() nounwind {
+define dso_local i8* @bat00() nounwind {
; LINUX-64-STATIC-LABEL: bat00:
; LINUX-64-STATIC: # %bb.0: # %entry
; LINUX-64-STATIC-NEXT: movq src@{{.*}}(%rip), %rax
@@ -7513,7 +7453,7 @@ entry:
ret i8* bitcast (i32* getelementptr ([131072 x i32], [131072 x i32]* @src, i32 0, i64 16) to i8*)
}
-define i8* @bxt00() nounwind {
+define dso_local i8* @bxt00() nounwind {
; LINUX-64-STATIC-LABEL: bxt00:
; LINUX-64-STATIC: # %bb.0: # %entry
; LINUX-64-STATIC-NEXT: movq xsrc@{{.*}}(%rip), %rax
@@ -7584,7 +7524,7 @@ entry:
ret i8* bitcast (i32* getelementptr ([32 x i32], [32 x i32]* @xsrc, i32 0, i64 16) to i8*)
}
-define i8* @bat01() nounwind {
+define dso_local i8* @bat01() nounwind {
; LINUX-64-STATIC-LABEL: bat01:
; LINUX-64-STATIC: # %bb.0: # %entry
; LINUX-64-STATIC-NEXT: movq dst@{{.*}}(%rip), %rax
@@ -7655,7 +7595,7 @@ entry:
ret i8* bitcast (i32* getelementptr ([131072 x i32], [131072 x i32]* @dst, i32 0, i64 16) to i8*)
}
-define i8* @bxt01() nounwind {
+define dso_local i8* @bxt01() nounwind {
; LINUX-64-STATIC-LABEL: bxt01:
; LINUX-64-STATIC: # %bb.0: # %entry
; LINUX-64-STATIC-NEXT: movq xdst@{{.*}}(%rip), %rax
@@ -7726,7 +7666,7 @@ entry:
ret i8* bitcast (i32* getelementptr ([32 x i32], [32 x i32]* @xdst, i32 0, i64 16) to i8*)
}
-define i8* @bat02() nounwind {
+define dso_local i8* @bat02() nounwind {
; LINUX-64-STATIC-LABEL: bat02:
; LINUX-64-STATIC: # %bb.0: # %entry
; LINUX-64-STATIC-NEXT: movq ptr@{{.*}}(%rip), %rax
@@ -7810,7 +7750,7 @@ entry:
ret i8* %2
}
-define i8* @bat03() nounwind {
+define dso_local i8* @bat03() nounwind {
; LINUX-64-STATIC-LABEL: bat03:
; LINUX-64-STATIC: # %bb.0: # %entry
; LINUX-64-STATIC-NEXT: movl $dsrc+64, %eax
@@ -7828,14 +7768,12 @@ define i8* @bat03() nounwind {
; LINUX-32-PIC-NEXT: popl %eax
; LINUX-32-PIC-NEXT: .Ltmp93:
; LINUX-32-PIC-NEXT: addl $_GLOBAL_OFFSET_TABLE_+(.Ltmp93-.L93$pb), %eax
-; LINUX-32-PIC-NEXT: movl dsrc at GOT(%eax), %eax
-; LINUX-32-PIC-NEXT: addl $64, %eax
+; LINUX-32-PIC-NEXT: leal .Ldsrc$local at GOTOFF+64(%eax), %eax
; LINUX-32-PIC-NEXT: retl
;
; LINUX-64-PIC-LABEL: bat03:
; LINUX-64-PIC: # %bb.0: # %entry
-; LINUX-64-PIC-NEXT: movq dsrc@{{.*}}(%rip), %rax
-; LINUX-64-PIC-NEXT: addq $64, %rax
+; LINUX-64-PIC-NEXT: leaq .Ldsrc$local+{{.*}}(%rip), %rax
; LINUX-64-PIC-NEXT: retq
;
; DARWIN-32-STATIC-LABEL: bat03:
@@ -7875,7 +7813,7 @@ entry:
ret i8* bitcast (i32* getelementptr ([131072 x i32], [131072 x i32]* @dsrc, i32 0, i64 16) to i8*)
}
-define i8* @bat04() nounwind {
+define dso_local i8* @bat04() nounwind {
; LINUX-64-STATIC-LABEL: bat04:
; LINUX-64-STATIC: # %bb.0: # %entry
; LINUX-64-STATIC-NEXT: movl $ddst+64, %eax
@@ -7893,14 +7831,12 @@ define i8* @bat04() nounwind {
; LINUX-32-PIC-NEXT: popl %eax
; LINUX-32-PIC-NEXT: .Ltmp94:
; LINUX-32-PIC-NEXT: addl $_GLOBAL_OFFSET_TABLE_+(.Ltmp94-.L94$pb), %eax
-; LINUX-32-PIC-NEXT: movl ddst at GOT(%eax), %eax
-; LINUX-32-PIC-NEXT: addl $64, %eax
+; LINUX-32-PIC-NEXT: leal .Lddst$local at GOTOFF+64(%eax), %eax
; LINUX-32-PIC-NEXT: retl
;
; LINUX-64-PIC-LABEL: bat04:
; LINUX-64-PIC: # %bb.0: # %entry
-; LINUX-64-PIC-NEXT: movq ddst@{{.*}}(%rip), %rax
-; LINUX-64-PIC-NEXT: addq $64, %rax
+; LINUX-64-PIC-NEXT: leaq .Lddst$local+{{.*}}(%rip), %rax
; LINUX-64-PIC-NEXT: retq
;
; DARWIN-32-STATIC-LABEL: bat04:
@@ -7940,7 +7876,7 @@ entry:
ret i8* bitcast (i32* getelementptr ([131072 x i32], [131072 x i32]* @ddst, i32 0, i64 16) to i8*)
}
-define i8* @bat05() nounwind {
+define dso_local i8* @bat05() nounwind {
; LINUX-64-STATIC-LABEL: bat05:
; LINUX-64-STATIC: # %bb.0: # %entry
; LINUX-64-STATIC-NEXT: movq {{.*}}(%rip), %rax
@@ -7960,15 +7896,13 @@ define i8* @bat05() nounwind {
; LINUX-32-PIC-NEXT: popl %eax
; LINUX-32-PIC-NEXT: .Ltmp95:
; LINUX-32-PIC-NEXT: addl $_GLOBAL_OFFSET_TABLE_+(.Ltmp95-.L95$pb), %eax
-; LINUX-32-PIC-NEXT: movl dptr at GOT(%eax), %eax
-; LINUX-32-PIC-NEXT: movl (%eax), %eax
+; LINUX-32-PIC-NEXT: movl .Ldptr$local at GOTOFF(%eax), %eax
; LINUX-32-PIC-NEXT: addl $64, %eax
; LINUX-32-PIC-NEXT: retl
;
; LINUX-64-PIC-LABEL: bat05:
; LINUX-64-PIC: # %bb.0: # %entry
-; LINUX-64-PIC-NEXT: movq dptr@{{.*}}(%rip), %rax
-; LINUX-64-PIC-NEXT: movq (%rax), %rax
+; LINUX-64-PIC-NEXT: movq .Ldptr${{.*}}(%rip), %rax
; LINUX-64-PIC-NEXT: addq $64, %rax
; LINUX-64-PIC-NEXT: retq
;
@@ -8018,7 +7952,7 @@ entry:
ret i8* %2
}
-define i8* @bat06() nounwind {
+define dso_local i8* @bat06() nounwind {
; LINUX-64-STATIC-LABEL: bat06:
; LINUX-64-STATIC: # %bb.0: # %entry
; LINUX-64-STATIC-NEXT: movl $lsrc+64, %eax
@@ -8081,7 +8015,7 @@ entry:
ret i8* bitcast (i32* getelementptr ([131072 x i32], [131072 x i32]* @lsrc, i32 0, i64 16) to i8*)
}
-define i8* @bat07() nounwind {
+define dso_local i8* @bat07() nounwind {
; LINUX-64-STATIC-LABEL: bat07:
; LINUX-64-STATIC: # %bb.0: # %entry
; LINUX-64-STATIC-NEXT: movl $ldst+64, %eax
@@ -8144,7 +8078,7 @@ entry:
ret i8* bitcast (i32* getelementptr ([131072 x i32], [131072 x i32]* @ldst, i32 0, i64 16) to i8*)
}
-define i8* @bat08() nounwind {
+define dso_local i8* @bat08() nounwind {
; LINUX-64-STATIC-LABEL: bat08:
; LINUX-64-STATIC: # %bb.0: # %entry
; LINUX-64-STATIC-NEXT: movq {{.*}}(%rip), %rax
@@ -8220,7 +8154,7 @@ entry:
ret i8* %2
}
-define i8* @bam00() nounwind {
+define dso_local i8* @bam00() nounwind {
; LINUX-64-STATIC-LABEL: bam00:
; LINUX-64-STATIC: # %bb.0: # %entry
; LINUX-64-STATIC-NEXT: movl $262144, %eax # imm = 0x40000
@@ -8291,7 +8225,7 @@ entry:
ret i8* bitcast (i32* getelementptr ([131072 x i32], [131072 x i32]* @src, i32 0, i64 65536) to i8*)
}
-define i8* @bam01() nounwind {
+define dso_local i8* @bam01() nounwind {
; LINUX-64-STATIC-LABEL: bam01:
; LINUX-64-STATIC: # %bb.0: # %entry
; LINUX-64-STATIC-NEXT: movl $262144, %eax # imm = 0x40000
@@ -8362,7 +8296,7 @@ entry:
ret i8* bitcast (i32* getelementptr ([131072 x i32], [131072 x i32]* @dst, i32 0, i64 65536) to i8*)
}
-define i8* @bxm01() nounwind {
+define dso_local i8* @bxm01() nounwind {
; LINUX-64-STATIC-LABEL: bxm01:
; LINUX-64-STATIC: # %bb.0: # %entry
; LINUX-64-STATIC-NEXT: movl $262144, %eax # imm = 0x40000
@@ -8433,7 +8367,7 @@ entry:
ret i8* bitcast (i32* getelementptr ([32 x i32], [32 x i32]* @xdst, i32 0, i64 65536) to i8*)
}
-define i8* @bam02() nounwind {
+define dso_local i8* @bam02() nounwind {
; LINUX-64-STATIC-LABEL: bam02:
; LINUX-64-STATIC: # %bb.0: # %entry
; LINUX-64-STATIC-NEXT: movq ptr@{{.*}}(%rip), %rcx
@@ -8517,7 +8451,7 @@ entry:
ret i8* %2
}
-define i8* @bam03() nounwind {
+define dso_local i8* @bam03() nounwind {
; LINUX-64-STATIC-LABEL: bam03:
; LINUX-64-STATIC: # %bb.0: # %entry
; LINUX-64-STATIC-NEXT: movl $dsrc+262144, %eax
@@ -8532,17 +8466,15 @@ define i8* @bam03() nounwind {
; LINUX-32-PIC: # %bb.0: # %entry
; LINUX-32-PIC-NEXT: calll .L103$pb
; LINUX-32-PIC-NEXT: .L103$pb:
-; LINUX-32-PIC-NEXT: popl %ecx
+; LINUX-32-PIC-NEXT: popl %eax
; LINUX-32-PIC-NEXT: .Ltmp103:
-; LINUX-32-PIC-NEXT: addl $_GLOBAL_OFFSET_TABLE_+(.Ltmp103-.L103$pb), %ecx
-; LINUX-32-PIC-NEXT: movl $262144, %eax # imm = 0x40000
-; LINUX-32-PIC-NEXT: addl dsrc at GOT(%ecx), %eax
+; LINUX-32-PIC-NEXT: addl $_GLOBAL_OFFSET_TABLE_+(.Ltmp103-.L103$pb), %eax
+; LINUX-32-PIC-NEXT: leal .Ldsrc$local at GOTOFF+262144(%eax), %eax
; LINUX-32-PIC-NEXT: retl
;
; LINUX-64-PIC-LABEL: bam03:
; LINUX-64-PIC: # %bb.0: # %entry
-; LINUX-64-PIC-NEXT: movl $262144, %eax # imm = 0x40000
-; LINUX-64-PIC-NEXT: addq dsrc@{{.*}}(%rip), %rax
+; LINUX-64-PIC-NEXT: leaq .Ldsrc$local+{{.*}}(%rip), %rax
; LINUX-64-PIC-NEXT: retq
;
; DARWIN-32-STATIC-LABEL: bam03:
@@ -8582,7 +8514,7 @@ entry:
ret i8* bitcast (i32* getelementptr ([131072 x i32], [131072 x i32]* @dsrc, i32 0, i64 65536) to i8*)
}
-define i8* @bam04() nounwind {
+define dso_local i8* @bam04() nounwind {
; LINUX-64-STATIC-LABEL: bam04:
; LINUX-64-STATIC: # %bb.0: # %entry
; LINUX-64-STATIC-NEXT: movl $ddst+262144, %eax
@@ -8597,17 +8529,15 @@ define i8* @bam04() nounwind {
; LINUX-32-PIC: # %bb.0: # %entry
; LINUX-32-PIC-NEXT: calll .L104$pb
; LINUX-32-PIC-NEXT: .L104$pb:
-; LINUX-32-PIC-NEXT: popl %ecx
+; LINUX-32-PIC-NEXT: popl %eax
; LINUX-32-PIC-NEXT: .Ltmp104:
-; LINUX-32-PIC-NEXT: addl $_GLOBAL_OFFSET_TABLE_+(.Ltmp104-.L104$pb), %ecx
-; LINUX-32-PIC-NEXT: movl $262144, %eax # imm = 0x40000
-; LINUX-32-PIC-NEXT: addl ddst at GOT(%ecx), %eax
+; LINUX-32-PIC-NEXT: addl $_GLOBAL_OFFSET_TABLE_+(.Ltmp104-.L104$pb), %eax
+; LINUX-32-PIC-NEXT: leal .Lddst$local at GOTOFF+262144(%eax), %eax
; LINUX-32-PIC-NEXT: retl
;
; LINUX-64-PIC-LABEL: bam04:
; LINUX-64-PIC: # %bb.0: # %entry
-; LINUX-64-PIC-NEXT: movl $262144, %eax # imm = 0x40000
-; LINUX-64-PIC-NEXT: addq ddst@{{.*}}(%rip), %rax
+; LINUX-64-PIC-NEXT: leaq .Lddst$local+{{.*}}(%rip), %rax
; LINUX-64-PIC-NEXT: retq
;
; DARWIN-32-STATIC-LABEL: bam04:
@@ -8647,7 +8577,7 @@ entry:
ret i8* bitcast (i32* getelementptr ([131072 x i32], [131072 x i32]* @ddst, i32 0, i64 65536) to i8*)
}
-define i8* @bam05() nounwind {
+define dso_local i8* @bam05() nounwind {
; LINUX-64-STATIC-LABEL: bam05:
; LINUX-64-STATIC: # %bb.0: # %entry
; LINUX-64-STATIC-NEXT: movl $262144, %eax # imm = 0x40000
@@ -8664,19 +8594,17 @@ define i8* @bam05() nounwind {
; LINUX-32-PIC: # %bb.0: # %entry
; LINUX-32-PIC-NEXT: calll .L105$pb
; LINUX-32-PIC-NEXT: .L105$pb:
-; LINUX-32-PIC-NEXT: popl %eax
+; LINUX-32-PIC-NEXT: popl %ecx
; LINUX-32-PIC-NEXT: .Ltmp105:
-; LINUX-32-PIC-NEXT: addl $_GLOBAL_OFFSET_TABLE_+(.Ltmp105-.L105$pb), %eax
-; LINUX-32-PIC-NEXT: movl dptr at GOT(%eax), %ecx
+; LINUX-32-PIC-NEXT: addl $_GLOBAL_OFFSET_TABLE_+(.Ltmp105-.L105$pb), %ecx
; LINUX-32-PIC-NEXT: movl $262144, %eax # imm = 0x40000
-; LINUX-32-PIC-NEXT: addl (%ecx), %eax
+; LINUX-32-PIC-NEXT: addl .Ldptr$local at GOTOFF(%ecx), %eax
; LINUX-32-PIC-NEXT: retl
;
; LINUX-64-PIC-LABEL: bam05:
; LINUX-64-PIC: # %bb.0: # %entry
-; LINUX-64-PIC-NEXT: movq dptr@{{.*}}(%rip), %rcx
; LINUX-64-PIC-NEXT: movl $262144, %eax # imm = 0x40000
-; LINUX-64-PIC-NEXT: addq (%rcx), %rax
+; LINUX-64-PIC-NEXT: addq .Ldptr${{.*}}(%rip), %rax
; LINUX-64-PIC-NEXT: retq
;
; DARWIN-32-STATIC-LABEL: bam05:
@@ -8725,7 +8653,7 @@ entry:
ret i8* %2
}
-define i8* @bam06() nounwind {
+define dso_local i8* @bam06() nounwind {
; LINUX-64-STATIC-LABEL: bam06:
; LINUX-64-STATIC: # %bb.0: # %entry
; LINUX-64-STATIC-NEXT: movl $lsrc+262144, %eax
@@ -8788,7 +8716,7 @@ entry:
ret i8* bitcast (i32* getelementptr ([131072 x i32], [131072 x i32]* @lsrc, i32 0, i64 65536) to i8*)
}
-define i8* @bam07() nounwind {
+define dso_local i8* @bam07() nounwind {
; LINUX-64-STATIC-LABEL: bam07:
; LINUX-64-STATIC: # %bb.0: # %entry
; LINUX-64-STATIC-NEXT: movl $ldst+262144, %eax
@@ -8851,7 +8779,7 @@ entry:
ret i8* bitcast (i32* getelementptr ([131072 x i32], [131072 x i32]* @ldst, i32 0, i64 65536) to i8*)
}
-define i8* @bam08() nounwind {
+define dso_local i8* @bam08() nounwind {
; LINUX-64-STATIC-LABEL: bam08:
; LINUX-64-STATIC: # %bb.0: # %entry
; LINUX-64-STATIC-NEXT: movl $262144, %eax # imm = 0x40000
@@ -8927,7 +8855,7 @@ entry:
ret i8* %2
}
-define i8* @cat00(i64 %i) nounwind {
+define dso_local i8* @cat00(i64 %i) nounwind {
; LINUX-64-STATIC-LABEL: cat00:
; LINUX-64-STATIC: # %bb.0: # %entry
; LINUX-64-STATIC-NEXT: movq src@{{.*}}(%rip), %rax
@@ -9006,7 +8934,7 @@ entry:
ret i8* %2
}
-define i8* @cxt00(i64 %i) nounwind {
+define dso_local i8* @cxt00(i64 %i) nounwind {
; LINUX-64-STATIC-LABEL: cxt00:
; LINUX-64-STATIC: # %bb.0: # %entry
; LINUX-64-STATIC-NEXT: movq xsrc@{{.*}}(%rip), %rax
@@ -9085,7 +9013,7 @@ entry:
ret i8* %2
}
-define i8* @cat01(i64 %i) nounwind {
+define dso_local i8* @cat01(i64 %i) nounwind {
; LINUX-64-STATIC-LABEL: cat01:
; LINUX-64-STATIC: # %bb.0: # %entry
; LINUX-64-STATIC-NEXT: movq dst@{{.*}}(%rip), %rax
@@ -9164,7 +9092,7 @@ entry:
ret i8* %2
}
-define i8* @cxt01(i64 %i) nounwind {
+define dso_local i8* @cxt01(i64 %i) nounwind {
; LINUX-64-STATIC-LABEL: cxt01:
; LINUX-64-STATIC: # %bb.0: # %entry
; LINUX-64-STATIC-NEXT: movq xdst@{{.*}}(%rip), %rax
@@ -9243,7 +9171,7 @@ entry:
ret i8* %2
}
-define i8* @cat02(i64 %i) nounwind {
+define dso_local i8* @cat02(i64 %i) nounwind {
; LINUX-64-STATIC-LABEL: cat02:
; LINUX-64-STATIC: # %bb.0: # %entry
; LINUX-64-STATIC-NEXT: movq ptr@{{.*}}(%rip), %rax
@@ -9333,7 +9261,7 @@ entry:
ret i8* %3
}
-define i8* @cat03(i64 %i) nounwind {
+define dso_local i8* @cat03(i64 %i) nounwind {
; LINUX-64-STATIC-LABEL: cat03:
; LINUX-64-STATIC: # %bb.0: # %entry
; LINUX-64-STATIC-NEXT: leaq dsrc+64(,%rdi,4), %rax
@@ -9353,13 +9281,12 @@ define i8* @cat03(i64 %i) nounwind {
; LINUX-32-PIC-NEXT: .Ltmp114:
; LINUX-32-PIC-NEXT: addl $_GLOBAL_OFFSET_TABLE_+(.Ltmp114-.L114$pb), %eax
; LINUX-32-PIC-NEXT: movl {{[0-9]+}}(%esp), %ecx
-; LINUX-32-PIC-NEXT: movl dsrc at GOT(%eax), %eax
-; LINUX-32-PIC-NEXT: leal 64(%eax,%ecx,4), %eax
+; LINUX-32-PIC-NEXT: leal .Ldsrc$local at GOTOFF+64(%eax,%ecx,4), %eax
; LINUX-32-PIC-NEXT: retl
;
; LINUX-64-PIC-LABEL: cat03:
; LINUX-64-PIC: # %bb.0: # %entry
-; LINUX-64-PIC-NEXT: movq dsrc@{{.*}}(%rip), %rax
+; LINUX-64-PIC-NEXT: leaq .Ldsrc${{.*}}(%rip), %rax
; LINUX-64-PIC-NEXT: leaq 64(%rax,%rdi,4), %rax
; LINUX-64-PIC-NEXT: retq
;
@@ -9409,7 +9336,7 @@ entry:
ret i8* %2
}
-define i8* @cat04(i64 %i) nounwind {
+define dso_local i8* @cat04(i64 %i) nounwind {
; LINUX-64-STATIC-LABEL: cat04:
; LINUX-64-STATIC: # %bb.0: # %entry
; LINUX-64-STATIC-NEXT: leaq ddst+64(,%rdi,4), %rax
@@ -9429,13 +9356,12 @@ define i8* @cat04(i64 %i) nounwind {
; LINUX-32-PIC-NEXT: .Ltmp115:
; LINUX-32-PIC-NEXT: addl $_GLOBAL_OFFSET_TABLE_+(.Ltmp115-.L115$pb), %eax
; LINUX-32-PIC-NEXT: movl {{[0-9]+}}(%esp), %ecx
-; LINUX-32-PIC-NEXT: movl ddst at GOT(%eax), %eax
-; LINUX-32-PIC-NEXT: leal 64(%eax,%ecx,4), %eax
+; LINUX-32-PIC-NEXT: leal .Lddst$local at GOTOFF+64(%eax,%ecx,4), %eax
; LINUX-32-PIC-NEXT: retl
;
; LINUX-64-PIC-LABEL: cat04:
; LINUX-64-PIC: # %bb.0: # %entry
-; LINUX-64-PIC-NEXT: movq ddst@{{.*}}(%rip), %rax
+; LINUX-64-PIC-NEXT: leaq .Lddst${{.*}}(%rip), %rax
; LINUX-64-PIC-NEXT: leaq 64(%rax,%rdi,4), %rax
; LINUX-64-PIC-NEXT: retq
;
@@ -9485,7 +9411,7 @@ entry:
ret i8* %2
}
-define i8* @cat05(i64 %i) nounwind {
+define dso_local i8* @cat05(i64 %i) nounwind {
; LINUX-64-STATIC-LABEL: cat05:
; LINUX-64-STATIC: # %bb.0: # %entry
; LINUX-64-STATIC-NEXT: movq {{.*}}(%rip), %rax
@@ -9506,16 +9432,14 @@ define i8* @cat05(i64 %i) nounwind {
; LINUX-32-PIC-NEXT: popl %eax
; LINUX-32-PIC-NEXT: .Ltmp116:
; LINUX-32-PIC-NEXT: addl $_GLOBAL_OFFSET_TABLE_+(.Ltmp116-.L116$pb), %eax
-; LINUX-32-PIC-NEXT: movl dptr at GOT(%eax), %eax
-; LINUX-32-PIC-NEXT: movl (%eax), %eax
; LINUX-32-PIC-NEXT: movl {{[0-9]+}}(%esp), %ecx
+; LINUX-32-PIC-NEXT: movl .Ldptr$local at GOTOFF(%eax), %eax
; LINUX-32-PIC-NEXT: leal 64(%eax,%ecx,4), %eax
; LINUX-32-PIC-NEXT: retl
;
; LINUX-64-PIC-LABEL: cat05:
; LINUX-64-PIC: # %bb.0: # %entry
-; LINUX-64-PIC-NEXT: movq dptr@{{.*}}(%rip), %rax
-; LINUX-64-PIC-NEXT: movq (%rax), %rax
+; LINUX-64-PIC-NEXT: movq .Ldptr${{.*}}(%rip), %rax
; LINUX-64-PIC-NEXT: leaq 64(%rax,%rdi,4), %rax
; LINUX-64-PIC-NEXT: retq
;
@@ -9569,7 +9493,7 @@ entry:
ret i8* %3
}
-define i8* @cat06(i64 %i) nounwind {
+define dso_local i8* @cat06(i64 %i) nounwind {
; LINUX-64-STATIC-LABEL: cat06:
; LINUX-64-STATIC: # %bb.0: # %entry
; LINUX-64-STATIC-NEXT: leaq lsrc+64(,%rdi,4), %rax
@@ -9644,7 +9568,7 @@ entry:
ret i8* %2
}
-define i8* @cat07(i64 %i) nounwind {
+define dso_local i8* @cat07(i64 %i) nounwind {
; LINUX-64-STATIC-LABEL: cat07:
; LINUX-64-STATIC: # %bb.0: # %entry
; LINUX-64-STATIC-NEXT: leaq ldst+64(,%rdi,4), %rax
@@ -9719,7 +9643,7 @@ entry:
ret i8* %2
}
-define i8* @cat08(i64 %i) nounwind {
+define dso_local i8* @cat08(i64 %i) nounwind {
; LINUX-64-STATIC-LABEL: cat08:
; LINUX-64-STATIC: # %bb.0: # %entry
; LINUX-64-STATIC-NEXT: movq {{.*}}(%rip), %rax
@@ -9801,7 +9725,7 @@ entry:
ret i8* %3
}
-define i8* @cam00(i64 %i) nounwind {
+define dso_local i8* @cam00(i64 %i) nounwind {
; LINUX-64-STATIC-LABEL: cam00:
; LINUX-64-STATIC: # %bb.0: # %entry
; LINUX-64-STATIC-NEXT: movq src@{{.*}}(%rip), %rax
@@ -9880,7 +9804,7 @@ entry:
ret i8* %2
}
-define i8* @cxm00(i64 %i) nounwind {
+define dso_local i8* @cxm00(i64 %i) nounwind {
; LINUX-64-STATIC-LABEL: cxm00:
; LINUX-64-STATIC: # %bb.0: # %entry
; LINUX-64-STATIC-NEXT: movq xsrc@{{.*}}(%rip), %rax
@@ -9959,7 +9883,7 @@ entry:
ret i8* %2
}
-define i8* @cam01(i64 %i) nounwind {
+define dso_local i8* @cam01(i64 %i) nounwind {
; LINUX-64-STATIC-LABEL: cam01:
; LINUX-64-STATIC: # %bb.0: # %entry
; LINUX-64-STATIC-NEXT: movq dst@{{.*}}(%rip), %rax
@@ -10038,7 +9962,7 @@ entry:
ret i8* %2
}
-define i8* @cxm01(i64 %i) nounwind {
+define dso_local i8* @cxm01(i64 %i) nounwind {
; LINUX-64-STATIC-LABEL: cxm01:
; LINUX-64-STATIC: # %bb.0: # %entry
; LINUX-64-STATIC-NEXT: movq xdst@{{.*}}(%rip), %rax
@@ -10117,7 +10041,7 @@ entry:
ret i8* %2
}
-define i8* @cam02(i64 %i) nounwind {
+define dso_local i8* @cam02(i64 %i) nounwind {
; LINUX-64-STATIC-LABEL: cam02:
; LINUX-64-STATIC: # %bb.0: # %entry
; LINUX-64-STATIC-NEXT: movq ptr@{{.*}}(%rip), %rax
@@ -10207,7 +10131,7 @@ entry:
ret i8* %3
}
-define i8* @cam03(i64 %i) nounwind {
+define dso_local i8* @cam03(i64 %i) nounwind {
; LINUX-64-STATIC-LABEL: cam03:
; LINUX-64-STATIC: # %bb.0: # %entry
; LINUX-64-STATIC-NEXT: leaq dsrc+262144(,%rdi,4), %rax
@@ -10227,13 +10151,12 @@ define i8* @cam03(i64 %i) nounwind {
; LINUX-32-PIC-NEXT: .Ltmp125:
; LINUX-32-PIC-NEXT: addl $_GLOBAL_OFFSET_TABLE_+(.Ltmp125-.L125$pb), %eax
; LINUX-32-PIC-NEXT: movl {{[0-9]+}}(%esp), %ecx
-; LINUX-32-PIC-NEXT: movl dsrc at GOT(%eax), %eax
-; LINUX-32-PIC-NEXT: leal 262144(%eax,%ecx,4), %eax
+; LINUX-32-PIC-NEXT: leal .Ldsrc$local at GOTOFF+262144(%eax,%ecx,4), %eax
; LINUX-32-PIC-NEXT: retl
;
; LINUX-64-PIC-LABEL: cam03:
; LINUX-64-PIC: # %bb.0: # %entry
-; LINUX-64-PIC-NEXT: movq dsrc@{{.*}}(%rip), %rax
+; LINUX-64-PIC-NEXT: leaq .Ldsrc${{.*}}(%rip), %rax
; LINUX-64-PIC-NEXT: leaq 262144(%rax,%rdi,4), %rax
; LINUX-64-PIC-NEXT: retq
;
@@ -10283,7 +10206,7 @@ entry:
ret i8* %2
}
-define i8* @cam04(i64 %i) nounwind {
+define dso_local i8* @cam04(i64 %i) nounwind {
; LINUX-64-STATIC-LABEL: cam04:
; LINUX-64-STATIC: # %bb.0: # %entry
; LINUX-64-STATIC-NEXT: leaq ddst+262144(,%rdi,4), %rax
@@ -10303,13 +10226,12 @@ define i8* @cam04(i64 %i) nounwind {
; LINUX-32-PIC-NEXT: .Ltmp126:
; LINUX-32-PIC-NEXT: addl $_GLOBAL_OFFSET_TABLE_+(.Ltmp126-.L126$pb), %eax
; LINUX-32-PIC-NEXT: movl {{[0-9]+}}(%esp), %ecx
-; LINUX-32-PIC-NEXT: movl ddst at GOT(%eax), %eax
-; LINUX-32-PIC-NEXT: leal 262144(%eax,%ecx,4), %eax
+; LINUX-32-PIC-NEXT: leal .Lddst$local at GOTOFF+262144(%eax,%ecx,4), %eax
; LINUX-32-PIC-NEXT: retl
;
; LINUX-64-PIC-LABEL: cam04:
; LINUX-64-PIC: # %bb.0: # %entry
-; LINUX-64-PIC-NEXT: movq ddst@{{.*}}(%rip), %rax
+; LINUX-64-PIC-NEXT: leaq .Lddst${{.*}}(%rip), %rax
; LINUX-64-PIC-NEXT: leaq 262144(%rax,%rdi,4), %rax
; LINUX-64-PIC-NEXT: retq
;
@@ -10359,7 +10281,7 @@ entry:
ret i8* %2
}
-define i8* @cam05(i64 %i) nounwind {
+define dso_local i8* @cam05(i64 %i) nounwind {
; LINUX-64-STATIC-LABEL: cam05:
; LINUX-64-STATIC: # %bb.0: # %entry
; LINUX-64-STATIC-NEXT: movq {{.*}}(%rip), %rax
@@ -10380,16 +10302,14 @@ define i8* @cam05(i64 %i) nounwind {
; LINUX-32-PIC-NEXT: popl %eax
; LINUX-32-PIC-NEXT: .Ltmp127:
; LINUX-32-PIC-NEXT: addl $_GLOBAL_OFFSET_TABLE_+(.Ltmp127-.L127$pb), %eax
-; LINUX-32-PIC-NEXT: movl dptr at GOT(%eax), %eax
-; LINUX-32-PIC-NEXT: movl (%eax), %eax
; LINUX-32-PIC-NEXT: movl {{[0-9]+}}(%esp), %ecx
+; LINUX-32-PIC-NEXT: movl .Ldptr$local at GOTOFF(%eax), %eax
; LINUX-32-PIC-NEXT: leal 262144(%eax,%ecx,4), %eax
; LINUX-32-PIC-NEXT: retl
;
; LINUX-64-PIC-LABEL: cam05:
; LINUX-64-PIC: # %bb.0: # %entry
-; LINUX-64-PIC-NEXT: movq dptr@{{.*}}(%rip), %rax
-; LINUX-64-PIC-NEXT: movq (%rax), %rax
+; LINUX-64-PIC-NEXT: movq .Ldptr${{.*}}(%rip), %rax
; LINUX-64-PIC-NEXT: leaq 262144(%rax,%rdi,4), %rax
; LINUX-64-PIC-NEXT: retq
;
@@ -10443,7 +10363,7 @@ entry:
ret i8* %3
}
-define i8* @cam06(i64 %i) nounwind {
+define dso_local i8* @cam06(i64 %i) nounwind {
; LINUX-64-STATIC-LABEL: cam06:
; LINUX-64-STATIC: # %bb.0: # %entry
; LINUX-64-STATIC-NEXT: leaq lsrc+262144(,%rdi,4), %rax
@@ -10518,7 +10438,7 @@ entry:
ret i8* %2
}
-define i8* @cam07(i64 %i) nounwind {
+define dso_local i8* @cam07(i64 %i) nounwind {
; LINUX-64-STATIC-LABEL: cam07:
; LINUX-64-STATIC: # %bb.0: # %entry
; LINUX-64-STATIC-NEXT: leaq ldst+262144(,%rdi,4), %rax
@@ -10593,7 +10513,7 @@ entry:
ret i8* %2
}
-define i8* @cam08(i64 %i) nounwind {
+define dso_local i8* @cam08(i64 %i) nounwind {
; LINUX-64-STATIC-LABEL: cam08:
; LINUX-64-STATIC: # %bb.0: # %entry
; LINUX-64-STATIC-NEXT: movq {{.*}}(%rip), %rax
@@ -10675,7 +10595,7 @@ entry:
ret i8* %3
}
-define void @lcallee() nounwind {
+define dso_local void @lcallee() nounwind {
; LINUX-64-STATIC-LABEL: lcallee:
; LINUX-64-STATIC: # %bb.0: # %entry
; LINUX-64-STATIC-NEXT: pushq %rax
@@ -10977,7 +10897,7 @@ entry:
declare void @y()
-define void ()* @address() nounwind {
+define dso_local void ()* @address() nounwind {
; LINUX-64-STATIC-LABEL: address:
; LINUX-64-STATIC: # %bb.0: # %entry
; LINUX-64-STATIC-NEXT: movq callee@{{.*}}(%rip), %rax
@@ -11042,7 +10962,7 @@ entry:
declare void @callee()
-define void ()* @laddress() nounwind {
+define dso_local void ()* @laddress() nounwind {
; LINUX-64-STATIC-LABEL: laddress:
; LINUX-64-STATIC: # %bb.0: # %entry
; LINUX-64-STATIC-NEXT: movl $lcallee, %eax
@@ -11060,12 +10980,12 @@ define void ()* @laddress() nounwind {
; LINUX-32-PIC-NEXT: popl %eax
; LINUX-32-PIC-NEXT: .Ltmp134:
; LINUX-32-PIC-NEXT: addl $_GLOBAL_OFFSET_TABLE_+(.Ltmp134-.L134$pb), %eax
-; LINUX-32-PIC-NEXT: movl lcallee at GOT(%eax), %eax
+; LINUX-32-PIC-NEXT: leal .Llcallee$local at GOTOFF(%eax), %eax
; LINUX-32-PIC-NEXT: retl
;
; LINUX-64-PIC-LABEL: laddress:
; LINUX-64-PIC: # %bb.0: # %entry
-; LINUX-64-PIC-NEXT: movq lcallee@{{.*}}(%rip), %rax
+; LINUX-64-PIC-NEXT: leaq .Llcallee${{.*}}(%rip), %rax
; LINUX-64-PIC-NEXT: retq
;
; DARWIN-32-STATIC-LABEL: laddress:
@@ -11105,7 +11025,7 @@ entry:
ret void ()* @lcallee
}
-define void ()* @daddress() nounwind {
+define dso_local void ()* @daddress() nounwind {
; LINUX-64-STATIC-LABEL: daddress:
; LINUX-64-STATIC: # %bb.0: # %entry
; LINUX-64-STATIC-NEXT: movl $dcallee, %eax
@@ -11168,7 +11088,7 @@ entry:
ret void ()* @dcallee
}
-define void @caller() nounwind {
+define dso_local void @caller() nounwind {
; LINUX-64-STATIC-LABEL: caller:
; LINUX-64-STATIC: # %bb.0: # %entry
; LINUX-64-STATIC-NEXT: pushq %rax
@@ -11262,7 +11182,7 @@ entry:
ret void
}
-define void @dcaller() nounwind {
+define dso_local void @dcaller() nounwind {
; LINUX-64-STATIC-LABEL: dcaller:
; LINUX-64-STATIC: # %bb.0: # %entry
; LINUX-64-STATIC-NEXT: pushq %rax
@@ -11356,7 +11276,7 @@ entry:
ret void
}
-define void @lcaller() nounwind {
+define dso_local void @lcaller() nounwind {
; LINUX-64-STATIC-LABEL: lcaller:
; LINUX-64-STATIC: # %bb.0: # %entry
; LINUX-64-STATIC-NEXT: pushq %rax
@@ -11382,8 +11302,8 @@ define void @lcaller() nounwind {
; LINUX-32-PIC-NEXT: popl %ebx
; LINUX-32-PIC-NEXT: .Ltmp138:
; LINUX-32-PIC-NEXT: addl $_GLOBAL_OFFSET_TABLE_+(.Ltmp138-.L138$pb), %ebx
-; LINUX-32-PIC-NEXT: calll lcallee at PLT
-; LINUX-32-PIC-NEXT: calll lcallee at PLT
+; LINUX-32-PIC-NEXT: calll .Llcallee$local
+; LINUX-32-PIC-NEXT: calll .Llcallee$local
; LINUX-32-PIC-NEXT: addl $8, %esp
; LINUX-32-PIC-NEXT: popl %ebx
; LINUX-32-PIC-NEXT: retl
@@ -11391,8 +11311,8 @@ define void @lcaller() nounwind {
; LINUX-64-PIC-LABEL: lcaller:
; LINUX-64-PIC: # %bb.0: # %entry
; LINUX-64-PIC-NEXT: pushq %rax
-; LINUX-64-PIC-NEXT: callq lcallee at PLT
-; LINUX-64-PIC-NEXT: callq lcallee at PLT
+; LINUX-64-PIC-NEXT: callq .Llcallee$local
+; LINUX-64-PIC-NEXT: callq .Llcallee$local
; LINUX-64-PIC-NEXT: popq %rax
; LINUX-64-PIC-NEXT: retq
;
@@ -11450,7 +11370,7 @@ entry:
ret void
}
-define void @tailcaller() nounwind {
+define dso_local void @tailcaller() nounwind {
; LINUX-64-STATIC-LABEL: tailcaller:
; LINUX-64-STATIC: # %bb.0: # %entry
; LINUX-64-STATIC-NEXT: pushq %rax
@@ -11533,7 +11453,7 @@ entry:
ret void
}
-define void @dtailcaller() nounwind {
+define dso_local void @dtailcaller() nounwind {
; LINUX-64-STATIC-LABEL: dtailcaller:
; LINUX-64-STATIC: # %bb.0: # %entry
; LINUX-64-STATIC-NEXT: pushq %rax
@@ -11616,7 +11536,7 @@ entry:
ret void
}
-define void @ltailcaller() nounwind {
+define dso_local void @ltailcaller() nounwind {
; LINUX-64-STATIC-LABEL: ltailcaller:
; LINUX-64-STATIC: # %bb.0: # %entry
; LINUX-64-STATIC-NEXT: pushq %rax
@@ -11640,7 +11560,7 @@ define void @ltailcaller() nounwind {
; LINUX-32-PIC-NEXT: popl %ebx
; LINUX-32-PIC-NEXT: .Ltmp141:
; LINUX-32-PIC-NEXT: addl $_GLOBAL_OFFSET_TABLE_+(.Ltmp141-.L141$pb), %ebx
-; LINUX-32-PIC-NEXT: calll lcallee at PLT
+; LINUX-32-PIC-NEXT: calll .Llcallee$local
; LINUX-32-PIC-NEXT: addl $8, %esp
; LINUX-32-PIC-NEXT: popl %ebx
; LINUX-32-PIC-NEXT: retl
@@ -11648,7 +11568,7 @@ define void @ltailcaller() nounwind {
; LINUX-64-PIC-LABEL: ltailcaller:
; LINUX-64-PIC: # %bb.0: # %entry
; LINUX-64-PIC-NEXT: pushq %rax
-; LINUX-64-PIC-NEXT: callq lcallee at PLT
+; LINUX-64-PIC-NEXT: callq .Llcallee$local
; LINUX-64-PIC-NEXT: popq %rax
; LINUX-64-PIC-NEXT: retq
;
@@ -11699,7 +11619,7 @@ entry:
ret void
}
-define void @icaller() nounwind {
+define dso_local void @icaller() nounwind {
; LINUX-64-STATIC-LABEL: icaller:
; LINUX-64-STATIC: # %bb.0: # %entry
; LINUX-64-STATIC-NEXT: pushq %rbx
@@ -11812,7 +11732,7 @@ entry:
ret void
}
-define void @dicaller() nounwind {
+define dso_local void @dicaller() nounwind {
; LINUX-64-STATIC-LABEL: dicaller:
; LINUX-64-STATIC: # %bb.0: # %entry
; LINUX-64-STATIC-NEXT: pushq %rax
@@ -11832,28 +11752,24 @@ define void @dicaller() nounwind {
; LINUX-32-PIC-LABEL: dicaller:
; LINUX-32-PIC: # %bb.0: # %entry
; LINUX-32-PIC-NEXT: pushl %ebx
-; LINUX-32-PIC-NEXT: pushl %esi
-; LINUX-32-PIC-NEXT: pushl %eax
+; LINUX-32-PIC-NEXT: subl $8, %esp
; LINUX-32-PIC-NEXT: calll .L143$pb
; LINUX-32-PIC-NEXT: .L143$pb:
; LINUX-32-PIC-NEXT: popl %ebx
; LINUX-32-PIC-NEXT: .Ltmp143:
; LINUX-32-PIC-NEXT: addl $_GLOBAL_OFFSET_TABLE_+(.Ltmp143-.L143$pb), %ebx
-; LINUX-32-PIC-NEXT: movl difunc at GOT(%ebx), %esi
-; LINUX-32-PIC-NEXT: calll *(%esi)
-; LINUX-32-PIC-NEXT: calll *(%esi)
-; LINUX-32-PIC-NEXT: addl $4, %esp
-; LINUX-32-PIC-NEXT: popl %esi
+; LINUX-32-PIC-NEXT: calll *.Ldifunc$local at GOTOFF(%ebx)
+; LINUX-32-PIC-NEXT: calll *.Ldifunc$local at GOTOFF(%ebx)
+; LINUX-32-PIC-NEXT: addl $8, %esp
; LINUX-32-PIC-NEXT: popl %ebx
; LINUX-32-PIC-NEXT: retl
;
; LINUX-64-PIC-LABEL: dicaller:
; LINUX-64-PIC: # %bb.0: # %entry
-; LINUX-64-PIC-NEXT: pushq %rbx
-; LINUX-64-PIC-NEXT: movq difunc@{{.*}}(%rip), %rbx
-; LINUX-64-PIC-NEXT: callq *(%rbx)
-; LINUX-64-PIC-NEXT: callq *(%rbx)
-; LINUX-64-PIC-NEXT: popq %rbx
+; LINUX-64-PIC-NEXT: pushq %rax
+; LINUX-64-PIC-NEXT: callq *.Ldifunc${{.*}}(%rip)
+; LINUX-64-PIC-NEXT: callq *.Ldifunc${{.*}}(%rip)
+; LINUX-64-PIC-NEXT: popq %rax
; LINUX-64-PIC-NEXT: retq
;
; DARWIN-32-STATIC-LABEL: dicaller:
@@ -11917,7 +11833,7 @@ entry:
ret void
}
-define void @licaller() nounwind {
+define dso_local void @licaller() nounwind {
; LINUX-64-STATIC-LABEL: licaller:
; LINUX-64-STATIC: # %bb.0: # %entry
; LINUX-64-STATIC-NEXT: pushq %rax
@@ -12018,7 +11934,7 @@ entry:
ret void
}
-define void @itailcaller() nounwind {
+define dso_local void @itailcaller() nounwind {
; LINUX-64-STATIC-LABEL: itailcaller:
; LINUX-64-STATIC: # %bb.0: # %entry
; LINUX-64-STATIC-NEXT: pushq %rbx
@@ -12131,7 +12047,7 @@ entry:
ret void
}
-define void @ditailcaller() nounwind {
+define dso_local void @ditailcaller() nounwind {
; LINUX-64-STATIC-LABEL: ditailcaller:
; LINUX-64-STATIC: # %bb.0: # %entry
; LINUX-64-STATIC-NEXT: pushq %rax
@@ -12155,8 +12071,7 @@ define void @ditailcaller() nounwind {
; LINUX-32-PIC-NEXT: popl %ebx
; LINUX-32-PIC-NEXT: .Ltmp146:
; LINUX-32-PIC-NEXT: addl $_GLOBAL_OFFSET_TABLE_+(.Ltmp146-.L146$pb), %ebx
-; LINUX-32-PIC-NEXT: movl difunc at GOT(%ebx), %eax
-; LINUX-32-PIC-NEXT: calll *(%eax)
+; LINUX-32-PIC-NEXT: calll *.Ldifunc$local at GOTOFF(%ebx)
; LINUX-32-PIC-NEXT: addl $8, %esp
; LINUX-32-PIC-NEXT: popl %ebx
; LINUX-32-PIC-NEXT: retl
@@ -12164,8 +12079,7 @@ define void @ditailcaller() nounwind {
; LINUX-64-PIC-LABEL: ditailcaller:
; LINUX-64-PIC: # %bb.0: # %entry
; LINUX-64-PIC-NEXT: pushq %rax
-; LINUX-64-PIC-NEXT: movq difunc@{{.*}}(%rip), %rax
-; LINUX-64-PIC-NEXT: callq *(%rax)
+; LINUX-64-PIC-NEXT: callq *.Ldifunc${{.*}}(%rip)
; LINUX-64-PIC-NEXT: popq %rax
; LINUX-64-PIC-NEXT: retq
;
@@ -12220,7 +12134,7 @@ entry:
ret void
}
-define void @litailcaller() nounwind {
+define dso_local void @litailcaller() nounwind {
; LINUX-64-STATIC-LABEL: litailcaller:
; LINUX-64-STATIC: # %bb.0: # %entry
; LINUX-64-STATIC-NEXT: pushq %rax
diff --git a/llvm/test/CodeGen/X86/atomic-fp.ll b/llvm/test/CodeGen/X86/atomic-fp.ll
index 28825dc0fc11..62296169e06d 100644
--- a/llvm/test/CodeGen/X86/atomic-fp.ll
+++ b/llvm/test/CodeGen/X86/atomic-fp.ll
@@ -10,7 +10,7 @@
; ----- FADD -----
-define void @fadd_32r(float* %loc, float %val) nounwind {
+define dso_local void @fadd_32r(float* %loc, float %val) nounwind {
; X86-NOSSE-LABEL: fadd_32r:
; X86-NOSSE: # %bb.0:
; X86-NOSSE-NEXT: subl $8, %esp
@@ -75,7 +75,7 @@ define void @fadd_32r(float* %loc, float %val) nounwind {
ret void
}
-define void @fadd_64r(double* %loc, double %val) nounwind {
+define dso_local void @fadd_64r(double* %loc, double %val) nounwind {
; X86-NOSSE-LABEL: fadd_64r:
; X86-NOSSE: # %bb.0:
; X86-NOSSE-NEXT: pushl %ebp
@@ -176,11 +176,11 @@ define void @fadd_64r(double* %loc, double %val) nounwind {
ret void
}
- at glob32 = global float 0.000000e+00, align 4
- at glob64 = global double 0.000000e+00, align 8
+ at glob32 = dso_local global float 0.000000e+00, align 4
+ at glob64 = dso_local global double 0.000000e+00, align 8
; Floating-point add to a global using an immediate.
-define void @fadd_32g() nounwind {
+define dso_local void @fadd_32g() nounwind {
; X86-NOSSE-LABEL: fadd_32g:
; X86-NOSSE: # %bb.0:
; X86-NOSSE-NEXT: subl $8, %esp
@@ -242,7 +242,7 @@ define void @fadd_32g() nounwind {
ret void
}
-define void @fadd_64g() nounwind {
+define dso_local void @fadd_64g() nounwind {
; X86-NOSSE-LABEL: fadd_64g:
; X86-NOSSE: # %bb.0:
; X86-NOSSE-NEXT: pushl %ebp
@@ -341,7 +341,7 @@ define void @fadd_64g() nounwind {
}
; Floating-point add to a hard-coded immediate location using an immediate.
-define void @fadd_32imm() nounwind {
+define dso_local void @fadd_32imm() nounwind {
; X86-NOSSE-LABEL: fadd_32imm:
; X86-NOSSE: # %bb.0:
; X86-NOSSE-NEXT: subl $8, %esp
@@ -405,7 +405,7 @@ define void @fadd_32imm() nounwind {
ret void
}
-define void @fadd_64imm() nounwind {
+define dso_local void @fadd_64imm() nounwind {
; X86-NOSSE-LABEL: fadd_64imm:
; X86-NOSSE: # %bb.0:
; X86-NOSSE-NEXT: pushl %ebp
@@ -506,7 +506,7 @@ define void @fadd_64imm() nounwind {
}
; Floating-point add to a stack location.
-define void @fadd_32stack() nounwind {
+define dso_local void @fadd_32stack() nounwind {
; X86-NOSSE-LABEL: fadd_32stack:
; X86-NOSSE: # %bb.0:
; X86-NOSSE-NEXT: subl $12, %esp
@@ -574,7 +574,7 @@ define void @fadd_32stack() nounwind {
ret void
}
-define void @fadd_64stack() nounwind {
+define dso_local void @fadd_64stack() nounwind {
; X86-NOSSE-LABEL: fadd_64stack:
; X86-NOSSE: # %bb.0:
; X86-NOSSE-NEXT: pushl %ebp
@@ -674,7 +674,7 @@ define void @fadd_64stack() nounwind {
ret void
}
-define void @fadd_array(i64* %arg, double %arg1, i64 %arg2) nounwind {
+define dso_local void @fadd_array(i64* %arg, double %arg1, i64 %arg2) nounwind {
; X86-NOSSE-LABEL: fadd_array:
; X86-NOSSE: # %bb.0: # %bb
; X86-NOSSE-NEXT: pushl %ebp
diff --git a/llvm/test/CodeGen/X86/avx-vzeroupper.ll b/llvm/test/CodeGen/X86/avx-vzeroupper.ll
index f46b3503d883..577ed3678732 100644
--- a/llvm/test/CodeGen/X86/avx-vzeroupper.ll
+++ b/llvm/test/CodeGen/X86/avx-vzeroupper.ll
@@ -9,8 +9,8 @@ declare dso_local i32 @foo()
declare dso_local <4 x float> @do_sse(<4 x float>)
declare dso_local <8 x float> @do_avx(<8 x float>)
declare dso_local <4 x float> @llvm.x86.avx.vextractf128.ps.256(<8 x float>, i8) nounwind readnone
- at x = common global <4 x float> zeroinitializer, align 16
- at g = common global <8 x float> zeroinitializer, align 32
+ at x = common dso_local global <4 x float> zeroinitializer, align 16
+ at g = common dso_local global <8 x float> zeroinitializer, align 32
;; Basic checking - don't emit any vzeroupper instruction
diff --git a/llvm/test/CodeGen/X86/avx2-gather.ll b/llvm/test/CodeGen/X86/avx2-gather.ll
index cf4a624ebf43..fc4f54d173be 100644
--- a/llvm/test/CodeGen/X86/avx2-gather.ll
+++ b/llvm/test/CodeGen/X86/avx2-gather.ll
@@ -146,7 +146,7 @@ define <2 x double> @test_mm_i32gather_pd(double *%a0, <2 x i64> %a1) {
ret <2 x double> %res
}
- at x = global [1024 x float] zeroinitializer, align 16
+ at x = dso_local global [1024 x float] zeroinitializer, align 16
define <4 x float> @gather_global(<4 x i64>, i32* nocapture readnone) {
; X32-LABEL: gather_global:
diff --git a/llvm/test/CodeGen/X86/avx512-gather-scatter-intrin.ll b/llvm/test/CodeGen/X86/avx512-gather-scatter-intrin.ll
index 376788cb79bf..1bddfd962285 100644
--- a/llvm/test/CodeGen/X86/avx512-gather-scatter-intrin.ll
+++ b/llvm/test/CodeGen/X86/avx512-gather-scatter-intrin.ll
@@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512f,+avx512bw,+avx512vl,+avx512dq | FileCheck %s
-define void @gather_mask_dps(<16 x i32> %ind, <16 x float> %src, i16 %mask, i8* %base, i8* %stbuf) {
+define dso_local void @gather_mask_dps(<16 x i32> %ind, <16 x float> %src, i16 %mask, i8* %base, i8* %stbuf) {
; CHECK-LABEL: gather_mask_dps:
; CHECK: # %bb.0:
; CHECK-NEXT: kmovd %edi, %k1
@@ -18,7 +18,7 @@ define void @gather_mask_dps(<16 x i32> %ind, <16 x float> %src, i16 %mask, i8*
ret void
}
-define void @gather_mask_dpd(<8 x i32> %ind, <8 x double> %src, i8 %mask, i8* %base, i8* %stbuf) {
+define dso_local void @gather_mask_dpd(<8 x i32> %ind, <8 x double> %src, i8 %mask, i8* %base, i8* %stbuf) {
; CHECK-LABEL: gather_mask_dpd:
; CHECK: # %bb.0:
; CHECK-NEXT: kmovd %edi, %k1
@@ -35,7 +35,7 @@ define void @gather_mask_dpd(<8 x i32> %ind, <8 x double> %src, i8 %mask, i8* %b
ret void
}
-define void @gather_mask_qps(<8 x i64> %ind, <8 x float> %src, i8 %mask, i8* %base, i8* %stbuf) {
+define dso_local void @gather_mask_qps(<8 x i64> %ind, <8 x float> %src, i8 %mask, i8* %base, i8* %stbuf) {
; CHECK-LABEL: gather_mask_qps:
; CHECK: # %bb.0:
; CHECK-NEXT: kmovd %edi, %k1
@@ -52,7 +52,7 @@ define void @gather_mask_qps(<8 x i64> %ind, <8 x float> %src, i8 %mask, i8* %ba
ret void
}
-define void @gather_mask_qpd(<8 x i64> %ind, <8 x double> %src, i8 %mask, i8* %base, i8* %stbuf) {
+define dso_local void @gather_mask_qpd(<8 x i64> %ind, <8 x double> %src, i8 %mask, i8* %base, i8* %stbuf) {
; CHECK-LABEL: gather_mask_qpd:
; CHECK: # %bb.0:
; CHECK-NEXT: kmovd %edi, %k1
@@ -72,7 +72,7 @@ define void @gather_mask_qpd(<8 x i64> %ind, <8 x double> %src, i8 %mask, i8* %b
;; Integer Gather/Scatter
;;
-define void @gather_mask_dd(<16 x i32> %ind, <16 x i32> %src, i16 %mask, i8* %base, i8* %stbuf) {
+define dso_local void @gather_mask_dd(<16 x i32> %ind, <16 x i32> %src, i16 %mask, i8* %base, i8* %stbuf) {
; CHECK-LABEL: gather_mask_dd:
; CHECK: # %bb.0:
; CHECK-NEXT: kmovd %edi, %k1
@@ -89,7 +89,7 @@ define void @gather_mask_dd(<16 x i32> %ind, <16 x i32> %src, i16 %mask, i8* %ba
ret void
}
-define void @gather_mask_qd(<8 x i64> %ind, <8 x i32> %src, i8 %mask, i8* %base, i8* %stbuf) {
+define dso_local void @gather_mask_qd(<8 x i64> %ind, <8 x i32> %src, i8 %mask, i8* %base, i8* %stbuf) {
; CHECK-LABEL: gather_mask_qd:
; CHECK: # %bb.0:
; CHECK-NEXT: kmovd %edi, %k1
@@ -106,7 +106,7 @@ define void @gather_mask_qd(<8 x i64> %ind, <8 x i32> %src, i8 %mask, i8* %base,
ret void
}
-define void @gather_mask_qq(<8 x i64> %ind, <8 x i64> %src, i8 %mask, i8* %base, i8* %stbuf) {
+define dso_local void @gather_mask_qq(<8 x i64> %ind, <8 x i64> %src, i8 %mask, i8* %base, i8* %stbuf) {
; CHECK-LABEL: gather_mask_qq:
; CHECK: # %bb.0:
; CHECK-NEXT: kmovd %edi, %k1
@@ -123,7 +123,7 @@ define void @gather_mask_qq(<8 x i64> %ind, <8 x i64> %src, i8 %mask, i8* %base,
ret void
}
-define void @gather_mask_dq(<8 x i32> %ind, <8 x i64> %src, i8 %mask, i8* %base, i8* %stbuf) {
+define dso_local void @gather_mask_dq(<8 x i32> %ind, <8 x i64> %src, i8 %mask, i8* %base, i8* %stbuf) {
; CHECK-LABEL: gather_mask_dq:
; CHECK: # %bb.0:
; CHECK-NEXT: kmovd %edi, %k1
@@ -140,7 +140,7 @@ define void @gather_mask_dq(<8 x i32> %ind, <8 x i64> %src, i8 %mask, i8* %base,
ret void
}
-define void @gather_mask_dpd_execdomain(<8 x i32> %ind, <8 x double> %src, i8 %mask, i8* %base, <8 x double>* %stbuf) {
+define dso_local void @gather_mask_dpd_execdomain(<8 x i32> %ind, <8 x double> %src, i8 %mask, i8* %base, <8 x double>* %stbuf) {
; CHECK-LABEL: gather_mask_dpd_execdomain:
; CHECK: # %bb.0:
; CHECK-NEXT: kmovd %edi, %k1
@@ -154,7 +154,7 @@ define void @gather_mask_dpd_execdomain(<8 x i32> %ind, <8 x double> %src, i8 %m
ret void
}
-define void @gather_mask_qpd_execdomain(<8 x i64> %ind, <8 x double> %src, i8 %mask, i8* %base, <8 x double>* %stbuf) {
+define dso_local void @gather_mask_qpd_execdomain(<8 x i64> %ind, <8 x double> %src, i8 %mask, i8* %base, <8 x double>* %stbuf) {
; CHECK-LABEL: gather_mask_qpd_execdomain:
; CHECK: # %bb.0:
; CHECK-NEXT: kmovd %edi, %k1
@@ -192,7 +192,7 @@ define <8 x float> @gather_mask_qps_execdomain(<8 x i64> %ind, <8 x float> %src,
ret <8 x float> %res
}
-define void @scatter_mask_dpd_execdomain(<8 x i32> %ind, <8 x double>* %src, i8 %mask, i8* %base, i8* %stbuf) {
+define dso_local void @scatter_mask_dpd_execdomain(<8 x i32> %ind, <8 x double>* %src, i8 %mask, i8* %base, i8* %stbuf) {
; CHECK-LABEL: scatter_mask_dpd_execdomain:
; CHECK: # %bb.0:
; CHECK-NEXT: kmovd %esi, %k1
@@ -206,7 +206,7 @@ define void @scatter_mask_dpd_execdomain(<8 x i32> %ind, <8 x double>* %src, i8
ret void
}
-define void @scatter_mask_qpd_execdomain(<8 x i64> %ind, <8 x double>* %src, i8 %mask, i8* %base, i8* %stbuf) {
+define dso_local void @scatter_mask_qpd_execdomain(<8 x i64> %ind, <8 x double>* %src, i8 %mask, i8* %base, i8* %stbuf) {
; CHECK-LABEL: scatter_mask_qpd_execdomain:
; CHECK: # %bb.0:
; CHECK-NEXT: kmovd %esi, %k1
@@ -220,7 +220,7 @@ define void @scatter_mask_qpd_execdomain(<8 x i64> %ind, <8 x double>* %src, i8
ret void
}
-define void @scatter_mask_dps_execdomain(<16 x i32> %ind, <16 x float>* %src, i16 %mask, i8* %base, i8* %stbuf) {
+define dso_local void @scatter_mask_dps_execdomain(<16 x i32> %ind, <16 x float>* %src, i16 %mask, i8* %base, i8* %stbuf) {
; CHECK-LABEL: scatter_mask_dps_execdomain:
; CHECK: # %bb.0:
; CHECK-NEXT: kmovd %esi, %k1
@@ -234,7 +234,7 @@ define void @scatter_mask_dps_execdomain(<16 x i32> %ind, <16 x float>* %src, i1
ret void
}
-define void @scatter_mask_qps_execdomain(<8 x i64> %ind, <8 x float>* %src, i8 %mask, i8* %base, i8* %stbuf) {
+define dso_local void @scatter_mask_qps_execdomain(<8 x i64> %ind, <8 x float>* %src, i8 %mask, i8* %base, i8* %stbuf) {
; CHECK-LABEL: scatter_mask_qps_execdomain:
; CHECK: # %bb.0:
; CHECK-NEXT: kmovd %esi, %k1
@@ -248,7 +248,7 @@ define void @scatter_mask_qps_execdomain(<8 x i64> %ind, <8 x float>* %src, i8 %
ret void
}
-define void @gather_qps(<8 x i64> %ind, <8 x float> %src, i8* %base, i8* %stbuf) {
+define dso_local void @gather_qps(<8 x i64> %ind, <8 x float> %src, i8* %base, i8* %stbuf) {
; CHECK-LABEL: gather_qps:
; CHECK: # %bb.0:
; CHECK-NEXT: kxnorw %k0, %k0, %k1
@@ -267,7 +267,7 @@ define void @gather_qps(<8 x i64> %ind, <8 x float> %src, i8* %base, i8* %stbuf)
declare void @llvm.x86.avx512.gatherpf.qps.512(i8, <8 x i64>, i8* , i32, i32);
declare void @llvm.x86.avx512.scatterpf.qps.512(i8, <8 x i64>, i8* , i32, i32);
-define void @prefetch(<8 x i64> %ind, i8* %base) {
+define dso_local void @prefetch(<8 x i64> %ind, i8* %base) {
; CHECK-LABEL: prefetch:
; CHECK: # %bb.0:
; CHECK-NEXT: kxnorw %k0, %k0, %k1
@@ -577,7 +577,7 @@ define <8 x i32> @test_int_x86_avx512_mask_gather3siv8_si(<8 x i32> %x0, i8* %x1
ret <8 x i32> %res2
}
-define void at test_int_x86_avx512_scatterdiv2_df(i8* %x0, i8 %x1, <2 x i64> %x2, <2 x double> %x3) {
+define dso_local void at test_int_x86_avx512_scatterdiv2_df(i8* %x0, i8 %x1, <2 x i64> %x2, <2 x double> %x3) {
; CHECK-LABEL: test_int_x86_avx512_scatterdiv2_df:
; CHECK: # %bb.0:
; CHECK-NEXT: kmovd %esi, %k1
@@ -592,7 +592,7 @@ define void at test_int_x86_avx512_scatterdiv2_df(i8* %x0, i8 %x1, <2 x i64> %x2, <
ret void
}
-define void at test_int_x86_avx512_scatterdiv2_di(i8* %x0, i8 %x1, <2 x i64> %x2, <2 x i64> %x3) {
+define dso_local void at test_int_x86_avx512_scatterdiv2_di(i8* %x0, i8 %x1, <2 x i64> %x2, <2 x i64> %x3) {
; CHECK-LABEL: test_int_x86_avx512_scatterdiv2_di:
; CHECK: # %bb.0:
; CHECK-NEXT: kmovd %esi, %k1
@@ -607,7 +607,7 @@ define void at test_int_x86_avx512_scatterdiv2_di(i8* %x0, i8 %x1, <2 x i64> %x2, <
ret void
}
-define void at test_int_x86_avx512_scatterdiv4_df(i8* %x0, i8 %x1, <4 x i64> %x2, <4 x double> %x3) {
+define dso_local void at test_int_x86_avx512_scatterdiv4_df(i8* %x0, i8 %x1, <4 x i64> %x2, <4 x double> %x3) {
; CHECK-LABEL: test_int_x86_avx512_scatterdiv4_df:
; CHECK: # %bb.0:
; CHECK-NEXT: kmovd %esi, %k1
@@ -623,7 +623,7 @@ define void at test_int_x86_avx512_scatterdiv4_df(i8* %x0, i8 %x1, <4 x i64> %x2, <
ret void
}
-define void at test_int_x86_avx512_scatterdiv4_di(i8* %x0, i8 %x1, <4 x i64> %x2, <4 x i64> %x3) {
+define dso_local void at test_int_x86_avx512_scatterdiv4_di(i8* %x0, i8 %x1, <4 x i64> %x2, <4 x i64> %x3) {
; CHECK-LABEL: test_int_x86_avx512_scatterdiv4_di:
; CHECK: # %bb.0:
; CHECK-NEXT: kmovd %esi, %k1
@@ -639,7 +639,7 @@ define void at test_int_x86_avx512_scatterdiv4_di(i8* %x0, i8 %x1, <4 x i64> %x2, <
ret void
}
-define void at test_int_x86_avx512_scatterdiv4_sf(i8* %x0, i8 %x1, <2 x i64> %x2, <4 x float> %x3) {
+define dso_local void at test_int_x86_avx512_scatterdiv4_sf(i8* %x0, i8 %x1, <2 x i64> %x2, <4 x float> %x3) {
; CHECK-LABEL: test_int_x86_avx512_scatterdiv4_sf:
; CHECK: # %bb.0:
; CHECK-NEXT: kmovd %esi, %k1
@@ -654,7 +654,7 @@ define void at test_int_x86_avx512_scatterdiv4_sf(i8* %x0, i8 %x1, <2 x i64> %x2, <
ret void
}
-define void at test_int_x86_avx512_scatterdiv4_si(i8* %x0, i8 %x1, <2 x i64> %x2, <4 x i32> %x3) {
+define dso_local void at test_int_x86_avx512_scatterdiv4_si(i8* %x0, i8 %x1, <2 x i64> %x2, <4 x i32> %x3) {
; CHECK-LABEL: test_int_x86_avx512_scatterdiv4_si:
; CHECK: # %bb.0:
; CHECK-NEXT: kmovd %esi, %k1
@@ -669,7 +669,7 @@ define void at test_int_x86_avx512_scatterdiv4_si(i8* %x0, i8 %x1, <2 x i64> %x2, <
ret void
}
-define void at test_int_x86_avx512_scatterdiv8_sf(i8* %x0, i8 %x1, <4 x i64> %x2, <4 x float> %x3) {
+define dso_local void at test_int_x86_avx512_scatterdiv8_sf(i8* %x0, i8 %x1, <4 x i64> %x2, <4 x float> %x3) {
; CHECK-LABEL: test_int_x86_avx512_scatterdiv8_sf:
; CHECK: # %bb.0:
; CHECK-NEXT: kmovd %esi, %k1
@@ -685,7 +685,7 @@ define void at test_int_x86_avx512_scatterdiv8_sf(i8* %x0, i8 %x1, <4 x i64> %x2, <
ret void
}
-define void at test_int_x86_avx512_scatterdiv8_si(i8* %x0, i8 %x1, <4 x i64> %x2, <4 x i32> %x3) {
+define dso_local void at test_int_x86_avx512_scatterdiv8_si(i8* %x0, i8 %x1, <4 x i64> %x2, <4 x i32> %x3) {
; CHECK-LABEL: test_int_x86_avx512_scatterdiv8_si:
; CHECK: # %bb.0:
; CHECK-NEXT: kmovd %esi, %k1
@@ -701,7 +701,7 @@ define void at test_int_x86_avx512_scatterdiv8_si(i8* %x0, i8 %x1, <4 x i64> %x2, <
ret void
}
-define void at test_int_x86_avx512_scattersiv2_df(i8* %x0, i8 %x1, <4 x i32> %x2, <2 x double> %x3) {
+define dso_local void at test_int_x86_avx512_scattersiv2_df(i8* %x0, i8 %x1, <4 x i32> %x2, <2 x double> %x3) {
; CHECK-LABEL: test_int_x86_avx512_scattersiv2_df:
; CHECK: # %bb.0:
; CHECK-NEXT: kmovd %esi, %k1
@@ -716,7 +716,7 @@ define void at test_int_x86_avx512_scattersiv2_df(i8* %x0, i8 %x1, <4 x i32> %x2, <
ret void
}
-define void at test_int_x86_avx512_scattersiv2_di(i8* %x0, i8 %x1, <4 x i32> %x2, <2 x i64> %x3) {
+define dso_local void at test_int_x86_avx512_scattersiv2_di(i8* %x0, i8 %x1, <4 x i32> %x2, <2 x i64> %x3) {
; CHECK-LABEL: test_int_x86_avx512_scattersiv2_di:
; CHECK: # %bb.0:
; CHECK-NEXT: kmovd %esi, %k1
@@ -731,7 +731,7 @@ define void at test_int_x86_avx512_scattersiv2_di(i8* %x0, i8 %x1, <4 x i32> %x2, <
ret void
}
-define void at test_int_x86_avx512_scattersiv4_df(i8* %x0, i8 %x1, <4 x i32> %x2, <4 x double> %x3) {
+define dso_local void at test_int_x86_avx512_scattersiv4_df(i8* %x0, i8 %x1, <4 x i32> %x2, <4 x double> %x3) {
; CHECK-LABEL: test_int_x86_avx512_scattersiv4_df:
; CHECK: # %bb.0:
; CHECK-NEXT: kmovd %esi, %k1
@@ -747,7 +747,7 @@ define void at test_int_x86_avx512_scattersiv4_df(i8* %x0, i8 %x1, <4 x i32> %x2, <
ret void
}
-define void at test_int_x86_avx512_scattersiv4_di(i8* %x0, i8 %x1, <4 x i32> %x2, <4 x i64> %x3) {
+define dso_local void at test_int_x86_avx512_scattersiv4_di(i8* %x0, i8 %x1, <4 x i32> %x2, <4 x i64> %x3) {
; CHECK-LABEL: test_int_x86_avx512_scattersiv4_di:
; CHECK: # %bb.0:
; CHECK-NEXT: kmovd %esi, %k1
@@ -763,7 +763,7 @@ define void at test_int_x86_avx512_scattersiv4_di(i8* %x0, i8 %x1, <4 x i32> %x2, <
ret void
}
-define void at test_int_x86_avx512_scattersiv4_sf(i8* %x0, i8 %x1, <4 x i32> %x2, <4 x float> %x3) {
+define dso_local void at test_int_x86_avx512_scattersiv4_sf(i8* %x0, i8 %x1, <4 x i32> %x2, <4 x float> %x3) {
; CHECK-LABEL: test_int_x86_avx512_scattersiv4_sf:
; CHECK: # %bb.0:
; CHECK-NEXT: kmovd %esi, %k1
@@ -778,7 +778,7 @@ define void at test_int_x86_avx512_scattersiv4_sf(i8* %x0, i8 %x1, <4 x i32> %x2, <
ret void
}
-define void at test_int_x86_avx512_scattersiv4_si(i8* %x0, i8 %x1, <4 x i32> %x2, <4 x i32> %x3) {
+define dso_local void at test_int_x86_avx512_scattersiv4_si(i8* %x0, i8 %x1, <4 x i32> %x2, <4 x i32> %x3) {
; CHECK-LABEL: test_int_x86_avx512_scattersiv4_si:
; CHECK: # %bb.0:
; CHECK-NEXT: kmovd %esi, %k1
@@ -793,7 +793,7 @@ define void at test_int_x86_avx512_scattersiv4_si(i8* %x0, i8 %x1, <4 x i32> %x2, <
ret void
}
-define void at test_int_x86_avx512_scattersiv8_sf(i8* %x0, i8 %x1, <8 x i32> %x2, <8 x float> %x3) {
+define dso_local void at test_int_x86_avx512_scattersiv8_sf(i8* %x0, i8 %x1, <8 x i32> %x2, <8 x float> %x3) {
; CHECK-LABEL: test_int_x86_avx512_scattersiv8_sf:
; CHECK: # %bb.0:
; CHECK-NEXT: kmovd %esi, %k1
@@ -808,7 +808,7 @@ define void at test_int_x86_avx512_scattersiv8_sf(i8* %x0, i8 %x1, <8 x i32> %x2, <
ret void
}
-define void at test_int_x86_avx512_scattersiv8_si(i8* %x0, i8 %x1, <8 x i32> %x2, <8 x i32> %x3) {
+define dso_local void at test_int_x86_avx512_scattersiv8_si(i8* %x0, i8 %x1, <8 x i32> %x2, <8 x i32> %x3) {
; CHECK-LABEL: test_int_x86_avx512_scattersiv8_si:
; CHECK: # %bb.0:
; CHECK-NEXT: kmovd %esi, %k1
@@ -823,7 +823,7 @@ define void at test_int_x86_avx512_scattersiv8_si(i8* %x0, i8 %x1, <8 x i32> %x2, <
ret void
}
-define void @scatter_mask_test(i8* %x0, <8 x i32> %x2, <8 x i32> %x3) {
+define dso_local void @scatter_mask_test(i8* %x0, <8 x i32> %x2, <8 x i32> %x3) {
; CHECK-LABEL: scatter_mask_test:
; CHECK: # %bb.0:
; CHECK-NEXT: kxnorw %k0, %k0, %k1
@@ -875,7 +875,7 @@ define <16 x float> @gather_mask_test(<16 x i32> %ind, <16 x float> %src, i8* %b
ret <16 x float> %res6
}
- at x = global [1024 x float] zeroinitializer, align 16
+ at x = dso_local global [1024 x float] zeroinitializer, align 16
define <8 x float> @gather_global(<8 x i64>, i32* nocapture readnone) {
; CHECK-LABEL: gather_global:
diff --git a/llvm/test/CodeGen/X86/avx512-regcall-Mask.ll b/llvm/test/CodeGen/X86/avx512-regcall-Mask.ll
index bbf495619dbd..799747b2aba6 100644
--- a/llvm/test/CodeGen/X86/avx512-regcall-Mask.ll
+++ b/llvm/test/CodeGen/X86/avx512-regcall-Mask.ll
@@ -4,7 +4,7 @@
; RUN: llc < %s -mtriple=x86_64-linux-gnu -mattr=+avx512bw | FileCheck %s --check-prefix=CHECK64 --check-prefix=LINUXOSX64
; Test regcall when receiving arguments of v64i1 type
-define x86_regcallcc i64 @test_argv64i1(<64 x i1> %x0, <64 x i1> %x1, <64 x i1> %x2, <64 x i1> %x3, <64 x i1> %x4, <64 x i1> %x5, <64 x i1> %x6, <64 x i1> %x7, <64 x i1> %x8, <64 x i1> %x9, <64 x i1> %x10, <64 x i1> %x11, <64 x i1> %x12) {
+define dso_local x86_regcallcc i64 @test_argv64i1(<64 x i1> %x0, <64 x i1> %x1, <64 x i1> %x2, <64 x i1> %x3, <64 x i1> %x4, <64 x i1> %x5, <64 x i1> %x6, <64 x i1> %x7, <64 x i1> %x8, <64 x i1> %x9, <64 x i1> %x10, <64 x i1> %x11, <64 x i1> %x12) {
; X32-LABEL: test_argv64i1:
; X32: # %bb.0:
; X32-NEXT: addl %edx, %eax
@@ -93,7 +93,7 @@ define x86_regcallcc i64 @test_argv64i1(<64 x i1> %x0, <64 x i1> %x1, <64 x i1>
}
; Test regcall when passing arguments of v64i1 type
-define i64 @caller_argv64i1() #0 {
+define dso_local i64 @caller_argv64i1() #0 {
; X32-LABEL: caller_argv64i1:
; X32: # %bb.0: # %entry
; X32-NEXT: pushl %edi
@@ -213,7 +213,7 @@ entry:
}
; Test regcall when returning v64i1 type
-define x86_regcallcc <64 x i1> @test_retv64i1() {
+define dso_local x86_regcallcc <64 x i1> @test_retv64i1() {
; X32-LABEL: test_retv64i1:
; X32: # %bb.0:
; X32-NEXT: movl $2, %eax
@@ -229,7 +229,7 @@ define x86_regcallcc <64 x i1> @test_retv64i1() {
}
; Test regcall when processing result of v64i1 type
-define <64 x i1> @caller_retv64i1() #0 {
+define dso_local <64 x i1> @caller_retv64i1() #0 {
; X32-LABEL: caller_retv64i1:
; X32: # %bb.0: # %entry
; X32-NEXT: calll _test_retv64i1
@@ -280,7 +280,7 @@ entry:
; Test regcall when receiving arguments of v32i1 type
declare i32 @test_argv32i1helper(<32 x i1> %x0, <32 x i1> %x1, <32 x i1> %x2)
-define x86_regcallcc i32 @test_argv32i1(<32 x i1> %x0, <32 x i1> %x1, <32 x i1> %x2) {
+define dso_local x86_regcallcc i32 @test_argv32i1(<32 x i1> %x0, <32 x i1> %x1, <32 x i1> %x2) {
; X32-LABEL: test_argv32i1:
; X32: # %bb.0: # %entry
; X32-NEXT: pushl %esp
@@ -379,7 +379,7 @@ define x86_regcallcc i32 @test_argv32i1(<32 x i1> %x0, <32 x i1> %x1, <32 x i1>
; LINUXOSX64-NEXT: # kill: def $ymm0 killed $ymm0 killed $zmm0
; LINUXOSX64-NEXT: # kill: def $ymm1 killed $ymm1 killed $zmm1
; LINUXOSX64-NEXT: # kill: def $ymm2 killed $ymm2 killed $zmm2
-; LINUXOSX64-NEXT: callq test_argv32i1helper
+; LINUXOSX64-NEXT: callq test_argv32i1helper at PLT
; LINUXOSX64-NEXT: vmovaps (%rsp), %xmm8 # 16-byte Reload
; LINUXOSX64-NEXT: vmovaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm9 # 16-byte Reload
; LINUXOSX64-NEXT: vmovaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm10 # 16-byte Reload
@@ -400,7 +400,7 @@ entry:
}
; Test regcall when passing arguments of v32i1 type
-define i32 @caller_argv32i1() #0 {
+define dso_local i32 @caller_argv32i1() #0 {
; X32-LABEL: caller_argv32i1:
; X32: # %bb.0: # %entry
; X32-NEXT: movl $1, %eax
@@ -452,7 +452,7 @@ entry:
}
; Test regcall when returning v32i1 type
-define x86_regcallcc <32 x i1> @test_retv32i1() {
+define dso_local x86_regcallcc <32 x i1> @test_retv32i1() {
; X32-LABEL: test_retv32i1:
; X32: # %bb.0:
; X32-NEXT: movl $1, %eax
@@ -467,7 +467,7 @@ define x86_regcallcc <32 x i1> @test_retv32i1() {
}
; Test regcall when processing result of v32i1 type
-define i32 @caller_retv32i1() #0 {
+define dso_local i32 @caller_retv32i1() #0 {
; X32-LABEL: caller_retv32i1:
; X32: # %bb.0: # %entry
; X32-NEXT: calll _test_retv32i1
@@ -515,7 +515,7 @@ entry:
; Test regcall when receiving arguments of v16i1 type
declare i16 @test_argv16i1helper(<16 x i1> %x0, <16 x i1> %x1, <16 x i1> %x2)
-define x86_regcallcc i16 @test_argv16i1(<16 x i1> %x0, <16 x i1> %x1, <16 x i1> %x2) {
+define dso_local x86_regcallcc i16 @test_argv16i1(<16 x i1> %x0, <16 x i1> %x1, <16 x i1> %x2) {
; X32-LABEL: test_argv16i1:
; X32: # %bb.0:
; X32-NEXT: pushl %esp
@@ -609,7 +609,7 @@ define x86_regcallcc i16 @test_argv16i1(<16 x i1> %x0, <16 x i1> %x1, <16 x i1>
; LINUXOSX64-NEXT: # kill: def $xmm1 killed $xmm1 killed $zmm1
; LINUXOSX64-NEXT: # kill: def $xmm2 killed $xmm2 killed $zmm2
; LINUXOSX64-NEXT: vzeroupper
-; LINUXOSX64-NEXT: callq test_argv16i1helper
+; LINUXOSX64-NEXT: callq test_argv16i1helper at PLT
; LINUXOSX64-NEXT: vmovaps (%rsp), %xmm8 # 16-byte Reload
; LINUXOSX64-NEXT: vmovaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm9 # 16-byte Reload
; LINUXOSX64-NEXT: vmovaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm10 # 16-byte Reload
@@ -628,7 +628,7 @@ define x86_regcallcc i16 @test_argv16i1(<16 x i1> %x0, <16 x i1> %x1, <16 x i1>
}
; Test regcall when passing arguments of v16i1 type
-define i16 @caller_argv16i1() #0 {
+define dso_local i16 @caller_argv16i1() #0 {
; X32-LABEL: caller_argv16i1:
; X32: # %bb.0: # %entry
; X32-NEXT: movl $1, %eax
@@ -680,7 +680,7 @@ entry:
}
; Test regcall when returning v16i1 type
-define x86_regcallcc <16 x i1> @test_retv16i1() {
+define dso_local x86_regcallcc <16 x i1> @test_retv16i1() {
; X32-LABEL: test_retv16i1:
; X32: # %bb.0:
; X32-NEXT: movw $1, %ax
@@ -695,7 +695,7 @@ define x86_regcallcc <16 x i1> @test_retv16i1() {
}
; Test regcall when processing result of v16i1 type
-define i16 @caller_retv16i1() #0 {
+define dso_local i16 @caller_retv16i1() #0 {
; X32-LABEL: caller_retv16i1:
; X32: # %bb.0: # %entry
; X32-NEXT: calll _test_retv16i1
@@ -749,7 +749,7 @@ entry:
; Test regcall when receiving arguments of v8i1 type
declare i8 @test_argv8i1helper(<8 x i1> %x0, <8 x i1> %x1, <8 x i1> %x2)
-define x86_regcallcc i8 @test_argv8i1(<8 x i1> %x0, <8 x i1> %x1, <8 x i1> %x2) {
+define dso_local x86_regcallcc i8 @test_argv8i1(<8 x i1> %x0, <8 x i1> %x1, <8 x i1> %x2) {
; X32-LABEL: test_argv8i1:
; X32: # %bb.0:
; X32-NEXT: pushl %esp
@@ -843,7 +843,7 @@ define x86_regcallcc i8 @test_argv8i1(<8 x i1> %x0, <8 x i1> %x1, <8 x i1> %x2)
; LINUXOSX64-NEXT: # kill: def $xmm1 killed $xmm1 killed $zmm1
; LINUXOSX64-NEXT: # kill: def $xmm2 killed $xmm2 killed $zmm2
; LINUXOSX64-NEXT: vzeroupper
-; LINUXOSX64-NEXT: callq test_argv8i1helper
+; LINUXOSX64-NEXT: callq test_argv8i1helper at PLT
; LINUXOSX64-NEXT: vmovaps (%rsp), %xmm8 # 16-byte Reload
; LINUXOSX64-NEXT: vmovaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm9 # 16-byte Reload
; LINUXOSX64-NEXT: vmovaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm10 # 16-byte Reload
@@ -862,7 +862,7 @@ define x86_regcallcc i8 @test_argv8i1(<8 x i1> %x0, <8 x i1> %x1, <8 x i1> %x2)
}
; Test regcall when passing arguments of v8i1 type
-define i8 @caller_argv8i1() #0 {
+define dso_local i8 @caller_argv8i1() #0 {
; X32-LABEL: caller_argv8i1:
; X32: # %bb.0: # %entry
; X32-NEXT: movl $1, %eax
@@ -914,7 +914,7 @@ entry:
}
; Test regcall when returning v8i1 type
-define x86_regcallcc <8 x i1> @test_retv8i1() {
+define dso_local x86_regcallcc <8 x i1> @test_retv8i1() {
; X32-LABEL: test_retv8i1:
; X32: # %bb.0:
; X32-NEXT: movb $1, %al
@@ -929,7 +929,7 @@ define x86_regcallcc <8 x i1> @test_retv8i1() {
}
; Test regcall when processing result of v8i1 type
-define <8 x i1> @caller_retv8i1() #0 {
+define dso_local <8 x i1> @caller_retv8i1() #0 {
; X32-LABEL: caller_retv8i1:
; X32: # %bb.0: # %entry
; X32-NEXT: calll _test_retv8i1
diff --git a/llvm/test/CodeGen/X86/avx512-regcall-NoMask.ll b/llvm/test/CodeGen/X86/avx512-regcall-NoMask.ll
index 1ab55e17ce05..c2f0ad62fd63 100644
--- a/llvm/test/CodeGen/X86/avx512-regcall-NoMask.ll
+++ b/llvm/test/CodeGen/X86/avx512-regcall-NoMask.ll
@@ -4,7 +4,7 @@
; RUN: llc < %s -mtriple=x86_64-linux-gnu -mattr=+avx512f -mattr=+avx512vl -mattr=+avx512bw -mattr=+avx512dq -verify-machineinstrs | FileCheck %s --check-prefix=LINUXOSX64
; Test regcall when receiving/returning i1
-define x86_regcallcc i1 @test_argReti1(i1 %a) {
+define dso_local x86_regcallcc i1 @test_argReti1(i1 %a) {
; X32-LABEL: test_argReti1:
; X32: # %bb.0:
; X32-NEXT: incb %al
@@ -27,7 +27,7 @@ define x86_regcallcc i1 @test_argReti1(i1 %a) {
}
; Test regcall when passing/retrieving i1
-define x86_regcallcc i1 @test_CallargReti1(i1 %a) {
+define dso_local x86_regcallcc i1 @test_CallargReti1(i1 %a) {
; X32-LABEL: test_CallargReti1:
; X32: # %bb.0:
; X32-NEXT: pushl %esp
@@ -70,7 +70,7 @@ define x86_regcallcc i1 @test_CallargReti1(i1 %a) {
}
; Test regcall when receiving/returning i8
-define x86_regcallcc i8 @test_argReti8(i8 %a) {
+define dso_local x86_regcallcc i8 @test_argReti8(i8 %a) {
; X32-LABEL: test_argReti8:
; X32: # %bb.0:
; X32-NEXT: incb %al
@@ -93,7 +93,7 @@ define x86_regcallcc i8 @test_argReti8(i8 %a) {
}
; Test regcall when passing/retrieving i8
-define x86_regcallcc i8 @test_CallargReti8(i8 %a) {
+define dso_local x86_regcallcc i8 @test_CallargReti8(i8 %a) {
; X32-LABEL: test_CallargReti8:
; X32: # %bb.0:
; X32-NEXT: pushl %esp
@@ -136,7 +136,7 @@ define x86_regcallcc i8 @test_CallargReti8(i8 %a) {
}
; Test regcall when receiving/returning i16
-define x86_regcallcc i16 @test_argReti16(i16 %a) {
+define dso_local x86_regcallcc i16 @test_argReti16(i16 %a) {
; X32-LABEL: test_argReti16:
; X32: # %bb.0:
; X32-NEXT: incl %eax
@@ -159,7 +159,7 @@ define x86_regcallcc i16 @test_argReti16(i16 %a) {
}
; Test regcall when passing/retrieving i16
-define x86_regcallcc i16 @test_CallargReti16(i16 %a) {
+define dso_local x86_regcallcc i16 @test_CallargReti16(i16 %a) {
; X32-LABEL: test_CallargReti16:
; X32: # %bb.0:
; X32-NEXT: pushl %esp
@@ -205,7 +205,7 @@ define x86_regcallcc i16 @test_CallargReti16(i16 %a) {
}
; Test regcall when receiving/returning i32
-define x86_regcallcc i32 @test_argReti32(i32 %a) {
+define dso_local x86_regcallcc i32 @test_argReti32(i32 %a) {
; X32-LABEL: test_argReti32:
; X32: # %bb.0:
; X32-NEXT: incl %eax
@@ -225,7 +225,7 @@ define x86_regcallcc i32 @test_argReti32(i32 %a) {
}
; Test regcall when passing/retrieving i32
-define x86_regcallcc i32 @test_CallargReti32(i32 %a) {
+define dso_local x86_regcallcc i32 @test_CallargReti32(i32 %a) {
; X32-LABEL: test_CallargReti32:
; X32: # %bb.0:
; X32-NEXT: pushl %esp
@@ -265,7 +265,7 @@ define x86_regcallcc i32 @test_CallargReti32(i32 %a) {
}
; Test regcall when receiving/returning i64
-define x86_regcallcc i64 @test_argReti64(i64 %a) {
+define dso_local x86_regcallcc i64 @test_argReti64(i64 %a) {
; X32-LABEL: test_argReti64:
; X32: # %bb.0:
; X32-NEXT: addl $3, %eax
@@ -288,7 +288,7 @@ define x86_regcallcc i64 @test_argReti64(i64 %a) {
}
; Test regcall when passing/retrieving i64
-define x86_regcallcc i64 @test_CallargReti64(i64 %a) {
+define dso_local x86_regcallcc i64 @test_CallargReti64(i64 %a) {
; X32-LABEL: test_CallargReti64:
; X32: # %bb.0:
; X32-NEXT: pushl %esp
@@ -330,7 +330,7 @@ define x86_regcallcc i64 @test_CallargReti64(i64 %a) {
}
; Test regcall when receiving/returning float
-define x86_regcallcc float @test_argRetFloat(float %a) {
+define dso_local x86_regcallcc float @test_argRetFloat(float %a) {
; X32-LABEL: test_argRetFloat:
; X32: # %bb.0:
; X32-NEXT: vaddss __real at 3f800000, %xmm0, %xmm0
@@ -350,7 +350,7 @@ define x86_regcallcc float @test_argRetFloat(float %a) {
}
; Test regcall when passing/retrieving float
-define x86_regcallcc float @test_CallargRetFloat(float %a) {
+define dso_local x86_regcallcc float @test_CallargRetFloat(float %a) {
; X32-LABEL: test_CallargRetFloat:
; X32: # %bb.0:
; X32-NEXT: pushl %esp
@@ -410,7 +410,7 @@ define x86_regcallcc float @test_CallargRetFloat(float %a) {
}
; Test regcall when receiving/returning double
-define x86_regcallcc double @test_argRetDouble(double %a) {
+define dso_local x86_regcallcc double @test_argRetDouble(double %a) {
; X32-LABEL: test_argRetDouble:
; X32: # %bb.0:
; X32-NEXT: vaddsd __real at 3ff0000000000000, %xmm0, %xmm0
@@ -430,7 +430,7 @@ define x86_regcallcc double @test_argRetDouble(double %a) {
}
; Test regcall when passing/retrieving double
-define x86_regcallcc double @test_CallargRetDouble(double %a) {
+define dso_local x86_regcallcc double @test_CallargRetDouble(double %a) {
; X32-LABEL: test_CallargRetDouble:
; X32: # %bb.0:
; X32-NEXT: pushl %esp
@@ -510,7 +510,7 @@ define x86_regcallcc x86_fp80 @test_argRetf80(x86_fp80 %a0) nounwind {
}
; Test regcall when receiving/returning long double
-define x86_regcallcc double @test_argParamf80(x86_fp80 %a0) nounwind {
+define dso_local x86_regcallcc double @test_argParamf80(x86_fp80 %a0) nounwind {
; X32-LABEL: test_argParamf80:
; X32: # %bb.0:
; X32-NEXT: pushl %ebp
@@ -580,7 +580,7 @@ define x86_regcallcc x86_fp80 @test_CallargRetf80(x86_fp80 %a) {
ret x86_fp80 %d
}
-define x86_regcallcc double @test_CallargParamf80(x86_fp80 %a) {
+define dso_local x86_regcallcc double @test_CallargParamf80(x86_fp80 %a) {
; X32-LABEL: test_CallargParamf80:
; X32: # %bb.0:
; X32-NEXT: pushl %esp
@@ -686,7 +686,7 @@ define x86_regcallcc [4 x i32]* @test_CallargRetPointer([4 x i32]* %a) {
}
; Test regcall when receiving/returning 128 bit vector
-define x86_regcallcc <4 x i32> @test_argRet128Vector(<4 x i1> %x, <4 x i32> %a, <4 x i32> %b) {
+define dso_local x86_regcallcc <4 x i32> @test_argRet128Vector(<4 x i1> %x, <4 x i32> %a, <4 x i32> %b) {
; X32-LABEL: test_argRet128Vector:
; X32: # %bb.0:
; X32-NEXT: vpslld $31, %xmm0, %xmm0
@@ -712,7 +712,7 @@ define x86_regcallcc <4 x i32> @test_argRet128Vector(<4 x i1> %x, <4 x i32> %a,
}
; Test regcall when passing/retrieving 128 bit vector
-define x86_regcallcc <4 x i32> @test_CallargRet128Vector(<4 x i1> %x, <4 x i32> %a) {
+define dso_local x86_regcallcc <4 x i32> @test_CallargRet128Vector(<4 x i1> %x, <4 x i32> %a) {
; X32-LABEL: test_CallargRet128Vector:
; X32: # %bb.0:
; X32-NEXT: pushl %esp
@@ -786,7 +786,7 @@ define x86_regcallcc <4 x i32> @test_CallargRet128Vector(<4 x i1> %x, <4 x i32>
}
; Test regcall when receiving/returning 256 bit vector
-define x86_regcallcc <8 x i32> @test_argRet256Vector(<8 x i1> %x, <8 x i32> %a, <8 x i32> %b) {
+define dso_local x86_regcallcc <8 x i32> @test_argRet256Vector(<8 x i1> %x, <8 x i32> %a, <8 x i32> %b) {
; X32-LABEL: test_argRet256Vector:
; X32: # %bb.0:
; X32-NEXT: kmovd %eax, %k1
@@ -809,7 +809,7 @@ define x86_regcallcc <8 x i32> @test_argRet256Vector(<8 x i1> %x, <8 x i32> %a,
}
; Test regcall when passing/retrieving 256 bit vector
-define x86_regcallcc <8 x i32> @test_CallargRet256Vector(<8 x i1> %x, <8 x i32> %a) {
+define dso_local x86_regcallcc <8 x i32> @test_CallargRet256Vector(<8 x i1> %x, <8 x i32> %a) {
; X32-LABEL: test_CallargRet256Vector:
; X32: # %bb.0:
; X32-NEXT: pushl %esp
@@ -872,7 +872,7 @@ define x86_regcallcc <8 x i32> @test_CallargRet256Vector(<8 x i1> %x, <8 x i32>
}
; Test regcall when receiving/returning 512 bit vector
-define x86_regcallcc <16 x i32> @test_argRet512Vector(<16 x i1> %x, <16 x i32> %a, <16 x i32> %b) {
+define dso_local x86_regcallcc <16 x i32> @test_argRet512Vector(<16 x i1> %x, <16 x i32> %a, <16 x i32> %b) {
; X32-LABEL: test_argRet512Vector:
; X32: # %bb.0:
; X32-NEXT: kmovd %eax, %k1
@@ -895,7 +895,7 @@ define x86_regcallcc <16 x i32> @test_argRet512Vector(<16 x i1> %x, <16 x i32> %
}
; Test regcall when passing/retrieving 512 bit vector
-define x86_regcallcc <16 x i32> @test_CallargRet512Vector(<16 x i1> %x, <16 x i32> %a) {
+define dso_local x86_regcallcc <16 x i32> @test_CallargRet512Vector(<16 x i1> %x, <16 x i32> %a) {
; X32-LABEL: test_CallargRet512Vector:
; X32: # %bb.0:
; X32-NEXT: pushl %esp
@@ -958,7 +958,7 @@ define x86_regcallcc <16 x i32> @test_CallargRet512Vector(<16 x i1> %x, <16 x i3
}
; Test regcall when running multiple input parameters - callee saved xmms
-define x86_regcallcc <32 x float> @testf32_inp(<32 x float> %a, <32 x float> %b, <32 x float> %c) nounwind {
+define dso_local x86_regcallcc <32 x float> @testf32_inp(<32 x float> %a, <32 x float> %b, <32 x float> %c) nounwind {
; X32-LABEL: testf32_inp:
; X32: # %bb.0:
; X32-NEXT: subl $44, %esp
@@ -1008,7 +1008,7 @@ define x86_regcallcc <32 x float> @testf32_inp(<32 x float> %a, <32 x float> %b,
}
; Test regcall when running multiple input parameters - callee saved GPRs
-define x86_regcallcc i32 @testi32_inp(i32 %a1, i32 %a2, i32 %a3, i32 %a4, i32 %a5, i32 %a6, i32 %b1, i32 %b2, i32 %b3, i32 %b4, i32 %b5, i32 %b6) nounwind {
+define dso_local x86_regcallcc i32 @testi32_inp(i32 %a1, i32 %a2, i32 %a3, i32 %a4, i32 %a5, i32 %a6, i32 %b1, i32 %b2, i32 %b3, i32 %b4, i32 %b5, i32 %b6) nounwind {
; X32-LABEL: testi32_inp:
; X32: # %bb.0:
; X32-NEXT: pushl %ebp
@@ -1163,7 +1163,7 @@ define x86_regcallcc i32 @testi32_inp(i32 %a1, i32 %a2, i32 %a3, i32 %a4, i32 %a
}
; Test that parameters, overflowing register capacity, are passed through the stack
-define x86_regcallcc <32 x float> @testf32_stack(<32 x float> %a0, <32 x float> %b0, <32 x float> %c0, <32 x float> %a1, <32 x float> %b1, <32 x float> %c1, <32 x float> %a2, <32 x float> %b2, <32 x float> %c2) nounwind {
+define dso_local x86_regcallcc <32 x float> @testf32_stack(<32 x float> %a0, <32 x float> %b0, <32 x float> %c0, <32 x float> %a1, <32 x float> %b1, <32 x float> %c1, <32 x float> %a2, <32 x float> %b2, <32 x float> %c2) nounwind {
; X32-LABEL: testf32_stack:
; X32: # %bb.0:
; X32-NEXT: pushl %ebp
@@ -1253,7 +1253,7 @@ define x86_regcallcc <32 x float> @testf32_stack(<32 x float> %a0, <32 x float>
}
; Test regcall when passing/retrieving mixed types
-define x86_regcallcc i32 @test_argRetMixTypes(double, float, i8 signext, i32, i64, i16 signext, i32*) #0 {
+define dso_local x86_regcallcc i32 @test_argRetMixTypes(double, float, i8 signext, i32, i64, i16 signext, i32*) #0 {
; X32-LABEL: test_argRetMixTypes:
; X32: # %bb.0:
; X32-NEXT: pushl %ebx
diff --git a/llvm/test/CodeGen/X86/backpropmask.ll b/llvm/test/CodeGen/X86/backpropmask.ll
index 50d43f6f03fc..602c2b7154e3 100644
--- a/llvm/test/CodeGen/X86/backpropmask.ll
+++ b/llvm/test/CodeGen/X86/backpropmask.ll
@@ -5,12 +5,12 @@
; nodes with multiple result values. In both tests, the stored
; 32-bit value should be masked to an 8-bit number (and 255).
- at b = local_unnamed_addr global i32 918, align 4
- at d = local_unnamed_addr global i32 8089, align 4
- at c = common local_unnamed_addr global i32 0, align 4
- at a = common local_unnamed_addr global i32 0, align 4
+ at b = dso_local local_unnamed_addr global i32 918, align 4
+ at d = dso_local local_unnamed_addr global i32 8089, align 4
+ at c = common dso_local local_unnamed_addr global i32 0, align 4
+ at a = common dso_local local_unnamed_addr global i32 0, align 4
-define void @PR37667() {
+define dso_local void @PR37667() {
; CHECK-LABEL: PR37667:
; CHECK: # %bb.0:
; CHECK-NEXT: movl {{.*}}(%rip), %eax
@@ -30,7 +30,7 @@ define void @PR37667() {
ret void
}
-define void @PR37060() {
+define dso_local void @PR37060() {
; CHECK-LABEL: PR37060:
; CHECK: # %bb.0:
; CHECK-NEXT: movl $-1, %eax
diff --git a/llvm/test/CodeGen/X86/break-false-dep.ll b/llvm/test/CodeGen/X86/break-false-dep.ll
index 9bc2b438caf0..7dd3bf11d57a 100644
--- a/llvm/test/CodeGen/X86/break-false-dep.ll
+++ b/llvm/test/CodeGen/X86/break-false-dep.ll
@@ -4,7 +4,7 @@
; RUN: llc < %s -mtriple=x86_64-win32 -mattr=+avx -mcpu=corei7-avx | FileCheck %s --check-prefixes=AVX,AVX1
; RUN: llc < %s -mtriple=x86_64-win32 -mattr=+avx512vl -mcpu=skx | FileCheck %s --check-prefixes=AVX,AVX512VL
-define double @t1(float* nocapture %x) nounwind readonly ssp {
+define dso_local double @t1(float* nocapture %x) nounwind readonly ssp {
; SSE-LABEL: t1:
; SSE: # %bb.0: # %entry
; SSE-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
@@ -23,7 +23,7 @@ entry:
ret double %1
}
-define float @t2(double* nocapture %x) nounwind readonly ssp optsize {
+define dso_local float @t2(double* nocapture %x) nounwind readonly ssp optsize {
; SSE-LINUX-LABEL: t2:
; SSE-LINUX: # %bb.0: # %entry
; SSE-LINUX-NEXT: cvtsd2ss (%rdi), %xmm0
@@ -44,7 +44,7 @@ entry:
ret float %1
}
-define float @squirtf(float* %x) nounwind {
+define dso_local float @squirtf(float* %x) nounwind {
; SSE-LABEL: squirtf:
; SSE: # %bb.0: # %entry
; SSE-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
@@ -62,7 +62,7 @@ entry:
ret float %t
}
-define double @squirt(double* %x) nounwind {
+define dso_local double @squirt(double* %x) nounwind {
; SSE-LABEL: squirt:
; SSE: # %bb.0: # %entry
; SSE-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
@@ -80,7 +80,7 @@ entry:
ret double %t
}
-define float @squirtf_size(float* %x) nounwind optsize {
+define dso_local float @squirtf_size(float* %x) nounwind optsize {
; SSE-LINUX-LABEL: squirtf_size:
; SSE-LINUX: # %bb.0: # %entry
; SSE-LINUX-NEXT: sqrtss (%rdi), %xmm0
@@ -101,7 +101,7 @@ entry:
ret float %t
}
-define double @squirt_size(double* %x) nounwind optsize {
+define dso_local double @squirt_size(double* %x) nounwind optsize {
; SSE-LINUX-LABEL: squirt_size:
; SSE-LINUX: # %bb.0: # %entry
; SSE-LINUX-NEXT: sqrtsd (%rdi), %xmm0
@@ -129,7 +129,7 @@ declare double @llvm.sqrt.f64(double)
; register. Verify that the break false dependency fix pass breaks those
; dependencies by inserting xorps instructions.
;
-define float @loopdep1(i32 %m) nounwind uwtable readnone ssp {
+define dso_local float @loopdep1(i32 %m) nounwind uwtable readnone ssp {
; SSE-LINUX-LABEL: loopdep1:
; SSE-LINUX: # %bb.0: # %entry
; SSE-LINUX-NEXT: testl %edi, %edi
@@ -408,13 +408,13 @@ ret:
; that follow it in the loop. Additionally, the source of convert is a
; memory operand. Verify the break false dependency fix pass breaks this
; dependency by inserting a xor before the convert.
- at x = common global [1024 x double] zeroinitializer, align 16
- at y = common global [1024 x double] zeroinitializer, align 16
- at z = common global [1024 x double] zeroinitializer, align 16
- at w = common global [1024 x double] zeroinitializer, align 16
- at v = common global [1024 x i32] zeroinitializer, align 16
+ at x = common dso_local global [1024 x double] zeroinitializer, align 16
+ at y = common dso_local global [1024 x double] zeroinitializer, align 16
+ at z = common dso_local global [1024 x double] zeroinitializer, align 16
+ at w = common dso_local global [1024 x double] zeroinitializer, align 16
+ at v = common dso_local global [1024 x i32] zeroinitializer, align 16
-define void @loopdep3() {
+define dso_local void @loopdep3() {
; SSE-LINUX-LABEL: loopdep3:
; SSE-LINUX: # %bb.0: # %entry
; SSE-LINUX-NEXT: xorl %eax, %eax
@@ -634,7 +634,7 @@ for.end16: ; preds = %for.inc14
}
-define double @inlineasmdep(i64 %arg) {
+define dso_local double @inlineasmdep(i64 %arg) {
; SSE-LINUX-LABEL: inlineasmdep:
; SSE-LINUX: # %bb.0: # %top
; SSE-LINUX-NEXT: #APP
@@ -785,7 +785,7 @@ top:
; Make sure we are making a smart choice regarding undef registers and
; hiding the false dependency behind a true dependency
-define double @truedeps(float %arg) {
+define dso_local double @truedeps(float %arg) {
; SSE-LINUX-LABEL: truedeps:
; SSE-LINUX: # %bb.0: # %top
; SSE-LINUX-NEXT: movss %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill
@@ -949,7 +949,7 @@ top:
; Make sure we are making a smart choice regarding undef registers and
; choosing the register with the highest clearence
-define double @clearence(i64 %arg) {
+define dso_local double @clearence(i64 %arg) {
; SSE-LINUX-LABEL: clearence:
; SSE-LINUX: # %bb.0: # %top
; SSE-LINUX-NEXT: #APP
@@ -1269,7 +1269,7 @@ ret:
; complicated loop structures. This example is the inner loop from
; julia> a = falses(10000); a[1:4:end] = true
; julia> linspace(1.0,2.0,10000)[a]
-define void @loopclearance2(double* nocapture %y, i64* %x, double %c1, double %c2, double %c3, double %c4, i64 %size) {
+define dso_local void @loopclearance2(double* nocapture %y, i64* %x, double %c1, double %c2, double %c3, double %c4, i64 %size) {
; SSE-LINUX-LABEL: loopclearance2:
; SSE-LINUX: # %bb.0: # %entry
; SSE-LINUX-NEXT: #APP
diff --git a/llvm/test/CodeGen/X86/bswap.ll b/llvm/test/CodeGen/X86/bswap.ll
index 89e5b3c86191..71497f06d7ed 100644
--- a/llvm/test/CodeGen/X86/bswap.ll
+++ b/llvm/test/CodeGen/X86/bswap.ll
@@ -25,7 +25,7 @@ define i16 @W(i16 %A) {
ret i16 %Z
}
-define i32 @X(i32 %A) {
+define dso_local i32 @X(i32 %A) {
; CHECK-LABEL: X:
; CHECK: # %bb.0:
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
@@ -66,7 +66,7 @@ define i64 @Y(i64 %A) {
; when the other ops have other uses (and it might not be safe
; either due to unconstrained instruction count growth).
-define i32 @bswap_multiuse(i32 %x, i32 %y, i32* %p1, i32* %p2) nounwind {
+define dso_local i32 @bswap_multiuse(i32 %x, i32 %y, i32* %p1, i32* %p2) nounwind {
; CHECK-LABEL: bswap_multiuse:
; CHECK: # %bb.0:
; CHECK-NEXT: pushl %esi
@@ -100,7 +100,7 @@ define i32 @bswap_multiuse(i32 %x, i32 %y, i32* %p1, i32* %p2) nounwind {
}
; rdar://9164521
-define i32 @test1(i32 %a) nounwind readnone {
+define dso_local i32 @test1(i32 %a) nounwind readnone {
; CHECK-LABEL: test1:
; CHECK: # %bb.0:
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
@@ -122,7 +122,7 @@ define i32 @test1(i32 %a) nounwind readnone {
ret i32 %or
}
-define i32 @test2(i32 %a) nounwind readnone {
+define dso_local i32 @test2(i32 %a) nounwind readnone {
; CHECK-LABEL: test2:
; CHECK: # %bb.0:
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
@@ -145,8 +145,8 @@ define i32 @test2(i32 %a) nounwind readnone {
ret i32 %conv3
}
- at var8 = global i8 0
- at var16 = global i16 0
+ at var8 = dso_local global i8 0
+ at var16 = dso_local global i16 0
; The "shl" below can move bits into the high parts of the value, so the
; operation is not a "bswap, shr" pair.
diff --git a/llvm/test/CodeGen/X86/callbr-asm-branch-folding.ll b/llvm/test/CodeGen/X86/callbr-asm-branch-folding.ll
index 3b3995891e90..768405104f1a 100644
--- a/llvm/test/CodeGen/X86/callbr-asm-branch-folding.ll
+++ b/llvm/test/CodeGen/X86/callbr-asm-branch-folding.ll
@@ -3,10 +3,10 @@
; This test hung in the BranchFolding pass during asm-goto bring up
- at e = global i32 0
- at j = global i32 0
+ at e = dso_local global i32 0
+ at j = dso_local global i32 0
-define void @n(i32* %o, i32 %p, i32 %u) nounwind {
+define dso_local void @n(i32* %o, i32 %p, i32 %u) nounwind {
; CHECK-LABEL: n:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: pushq %rbp
diff --git a/llvm/test/CodeGen/X86/cast-vsel.ll b/llvm/test/CodeGen/X86/cast-vsel.ll
index b4697d613ccc..709eeb1d8d3f 100644
--- a/llvm/test/CodeGen/X86/cast-vsel.ll
+++ b/llvm/test/CodeGen/X86/cast-vsel.ll
@@ -270,13 +270,13 @@ define <4 x float> @fptrunc(<4 x float> %a, <4 x float> %b, <4 x double> %c, <4
; These tests demonstrate the same issue as the simpler cases above,
; but also include multi-BB to show potentially larger transforms/codegen issues.
- at da = common global [1024 x float] zeroinitializer, align 32
- at db = common global [1024 x float] zeroinitializer, align 32
- at dc = common global [1024 x float] zeroinitializer, align 32
- at dd = common global [1024 x float] zeroinitializer, align 32
- at dj = common global [1024 x i32] zeroinitializer, align 32
+ at da = common dso_local global [1024 x float] zeroinitializer, align 32
+ at db = common dso_local global [1024 x float] zeroinitializer, align 32
+ at dc = common dso_local global [1024 x float] zeroinitializer, align 32
+ at dd = common dso_local global [1024 x float] zeroinitializer, align 32
+ at dj = common dso_local global [1024 x i32] zeroinitializer, align 32
-define void @example25() nounwind {
+define dso_local void @example25() nounwind {
; SSE2-LABEL: example25:
; SSE2: # %bb.0: # %vector.ph
; SSE2-NEXT: movq $-4096, %rax # imm = 0xF000
@@ -408,7 +408,7 @@ for.end:
; TODO: AVX1 could have used 256-bit ops for a likely improvement.
-define void @example24(i16 signext %x, i16 signext %y) nounwind {
+define dso_local void @example24(i16 signext %x, i16 signext %y) nounwind {
; SSE2-LABEL: example24:
; SSE2: # %bb.0: # %vector.ph
; SSE2-NEXT: movd %edi, %xmm0
diff --git a/llvm/test/CodeGen/X86/cmov-double.ll b/llvm/test/CodeGen/X86/cmov-double.ll
index f38b5e58ea5a..b63a35fff5ba 100644
--- a/llvm/test/CodeGen/X86/cmov-double.ll
+++ b/llvm/test/CodeGen/X86/cmov-double.ll
@@ -5,7 +5,7 @@ target triple = "x86_64-unknown-unknown"
; select with and i1/or i1 condition should be implemented as a series of 2
; cmovs, not by producing two conditions and using and on them.
-define i32 @select_and(i32 %a0, i32 %a1, float %a2, float %a3, i32 %a4, i32 %a5) {
+define dso_local i32 @select_and(i32 %a0, i32 %a1, float %a2, float %a3, i32 %a4, i32 %a5) {
; CHECK-LABEL: select_and:
; CHECK: # %bb.0:
; CHECK-NEXT: movl %edx, %eax
@@ -24,7 +24,7 @@ define i32 @select_and(i32 %a0, i32 %a1, float %a2, float %a3, i32 %a4, i32 %a5)
; select with and i1 condition should be implemented as a series of 2 cmovs, not
; by producing two conditions and using and on them.
-define i32 @select_or(i32 %a0, i32 %a1, float %a2, float %a3, i32 %a4, i32 %a5) {
+define dso_local i32 @select_or(i32 %a0, i32 %a1, float %a2, float %a3, i32 %a4, i32 %a5) {
; CHECK-LABEL: select_or:
; CHECK: # %bb.0:
; CHECK-NEXT: movl %ecx, %eax
@@ -43,8 +43,8 @@ define i32 @select_or(i32 %a0, i32 %a1, float %a2, float %a3, i32 %a4, i32 %a5)
; If one of the conditions is materialized as a 0/1 value anyway, then the
; sequence of 2 cmovs should not be used.
- at var32 = global i32 0
-define i32 @select_noopt(i32 %a0, i32 %a1, i32 %a2, i32 %a3, i32 %a4) {
+ at var32 = dso_local global i32 0
+define dso_local i32 @select_noopt(i32 %a0, i32 %a1, i32 %a2, i32 %a3, i32 %a4) {
; CHECK-LABEL: select_noopt:
; CHECK: # %bb.0:
; CHECK-NEXT: movl %ecx, %eax
diff --git a/llvm/test/CodeGen/X86/cmovcmov.ll b/llvm/test/CodeGen/X86/cmovcmov.ll
index c4ad9189aeaf..374da4468223 100644
--- a/llvm/test/CodeGen/X86/cmovcmov.ll
+++ b/llvm/test/CodeGen/X86/cmovcmov.ll
@@ -8,7 +8,7 @@ target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128"
; One way to do that is with (select (fcmp une/oeq)), which gets
; legalized to setp/setne.
-define i32 @test_select_fcmp_oeq_i32(float %a, float %b, i32 %c, i32 %d) nounwind {
+define dso_local i32 @test_select_fcmp_oeq_i32(float %a, float %b, i32 %c, i32 %d) nounwind {
; CMOV-LABEL: test_select_fcmp_oeq_i32:
; CMOV: # %bb.0: # %entry
; CMOV-NEXT: movl %edi, %eax
@@ -106,7 +106,7 @@ entry:
ret i64 %r
}
-define double @test_select_fcmp_oeq_f64(float %a, float %b, double %c, double %d) nounwind {
+define dso_local double @test_select_fcmp_oeq_f64(float %a, float %b, double %c, double %d) nounwind {
; CMOV-LABEL: test_select_fcmp_oeq_f64:
; CMOV: # %bb.0: # %entry
; CMOV-NEXT: ucomiss %xmm1, %xmm0
@@ -213,7 +213,7 @@ entry:
; Also make sure we catch the original code-sequence of interest:
-define float @test_zext_fcmp_une(float %a, float %b) nounwind {
+define dso_local float @test_zext_fcmp_une(float %a, float %b) nounwind {
; CMOV-LABEL: test_zext_fcmp_une:
; CMOV: # %bb.0: # %entry
; CMOV-NEXT: cmpneqss %xmm1, %xmm0
@@ -251,7 +251,7 @@ entry:
ret float %conv2
}
-define float @test_zext_fcmp_oeq(float %a, float %b) nounwind {
+define dso_local float @test_zext_fcmp_oeq(float %a, float %b) nounwind {
; CMOV-LABEL: test_zext_fcmp_oeq:
; CMOV: # %bb.0: # %entry
; CMOV-NEXT: cmpeqss %xmm1, %xmm0
@@ -291,7 +291,7 @@ entry:
attributes #0 = { nounwind }
- at g8 = global i8 0
+ at g8 = dso_local global i8 0
; The following test failed because llvm had a bug where a structure like:
;
@@ -311,7 +311,7 @@ attributes #0 = { nounwind }
; %13 = COPY %12
; Which was invalid as %12 is not the same value as %13
-define void @no_cascade_opt(i32 %v0, i32 %v1, i32 %v2, i32 %v3) nounwind {
+define dso_local void @no_cascade_opt(i32 %v0, i32 %v1, i32 %v2, i32 %v3) nounwind {
; CMOV-LABEL: no_cascade_opt:
; CMOV: # %bb.0: # %entry
; CMOV-NEXT: cmpl %edx, %esi
diff --git a/llvm/test/CodeGen/X86/cmp.ll b/llvm/test/CodeGen/X86/cmp.ll
index 1fe1fc05077a..ce441bbcc388 100644
--- a/llvm/test/CodeGen/X86/cmp.ll
+++ b/llvm/test/CodeGen/X86/cmp.ll
@@ -1,9 +1,9 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -show-mc-encoding | FileCheck %s
- at d = global i8 0, align 1
+ at d = dso_local global i8 0, align 1
-define i32 @test1(i32 %X, i32* %y) nounwind {
+define dso_local i32 @test1(i32 %X, i32* %y) nounwind {
; CHECK-LABEL: test1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: cmpl $0, (%rsi) # encoding: [0x83,0x3e,0x00]
@@ -27,7 +27,7 @@ ReturnBlock:
ret i32 0
}
-define i32 @test2(i32 %X, i32* %y) nounwind {
+define dso_local i32 @test2(i32 %X, i32* %y) nounwind {
; CHECK-LABEL: test2:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: testl $536870911, (%rsi) # encoding: [0xf7,0x06,0xff,0xff,0xff,0x1f]
@@ -53,7 +53,7 @@ ReturnBlock:
ret i32 0
}
-define i8 @test2b(i8 %X, i8* %y) nounwind {
+define dso_local i8 @test2b(i8 %X, i8* %y) nounwind {
; CHECK-LABEL: test2b:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: testb $31, (%rsi) # encoding: [0xf6,0x06,0x1f]
@@ -104,7 +104,7 @@ entry:
ret i64 %r
}
-define i32 @test5(double %A) nounwind {
+define dso_local i32 @test5(double %A) nounwind {
; CHECK-LABEL: test5:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: ucomisd {{.*}}(%rip), %xmm0 # encoding: [0x66,0x0f,0x2e,0x05,A,A,A,A]
@@ -140,7 +140,7 @@ bb12:
declare dso_local i32 @foo(...)
-define i32 @test6() nounwind align 2 {
+define dso_local i32 @test6() nounwind align 2 {
; CHECK-LABEL: test6:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: cmpq $0, -{{[0-9]+}}(%rsp) # encoding: [0x48,0x83,0x7c,0x24,0xf8,0x00]
@@ -166,7 +166,7 @@ F:
ret i32 0
}
-define i32 @test7(i64 %res) nounwind {
+define dso_local i32 @test7(i64 %res) nounwind {
; CHECK-LABEL: test7:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0]
@@ -179,7 +179,7 @@ entry:
ret i32 %lnot.ext
}
-define i32 @test8(i64 %res) nounwind {
+define dso_local i32 @test8(i64 %res) nounwind {
; CHECK-LABEL: test8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: shrq $32, %rdi # encoding: [0x48,0xc1,0xef,0x20]
@@ -193,7 +193,7 @@ entry:
ret i32 %lnot.ext
}
-define i32 @test9(i64 %res) nounwind {
+define dso_local i32 @test9(i64 %res) nounwind {
; CHECK-LABEL: test9:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0]
@@ -206,7 +206,7 @@ entry:
ret i32 %lnot.ext
}
-define i32 @test10(i64 %res) nounwind {
+define dso_local i32 @test10(i64 %res) nounwind {
; CHECK-LABEL: test10:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0]
@@ -219,7 +219,7 @@ entry:
ret i32 %lnot.ext
}
-define i32 @test11(i64 %l) nounwind {
+define dso_local i32 @test11(i64 %l) nounwind {
; CHECK-LABEL: test11:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: shrq $47, %rdi # encoding: [0x48,0xc1,0xef,0x2f]
@@ -234,7 +234,7 @@ entry:
ret i32 %conv
}
-define i32 @test12() ssp uwtable {
+define dso_local i32 @test12() ssp uwtable {
; CHECK-LABEL: test12:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: pushq %rax # encoding: [0x50]
@@ -268,7 +268,7 @@ F:
declare dso_local zeroext i1 @test12b()
-define i32 @test13(i32 %mask, i32 %base, i32 %intra) {
+define dso_local i32 @test13(i32 %mask, i32 %base, i32 %intra) {
; CHECK-LABEL: test13:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: movl %esi, %eax # encoding: [0x89,0xf0]
@@ -283,7 +283,7 @@ entry:
}
-define i32 @test14(i32 %mask, i32 %base, i32 %intra) {
+define dso_local i32 @test14(i32 %mask, i32 %base, i32 %intra) {
; CHECK-LABEL: test14:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: movl %esi, %eax # encoding: [0x89,0xf0]
@@ -317,7 +317,7 @@ entry:
}
-define i8 @test16(i16 signext %L) {
+define dso_local i8 @test16(i16 signext %L) {
; CHECK-LABEL: test16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: testw %di, %di # encoding: [0x66,0x85,0xff]
@@ -331,7 +331,7 @@ entry:
}
-define i8 @test17(i32 %L) {
+define dso_local i8 @test17(i32 %L) {
; CHECK-LABEL: test17:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: testl %edi, %edi # encoding: [0x85,0xff]
@@ -345,7 +345,7 @@ entry:
}
-define i8 @test18(i64 %L) {
+define dso_local i8 @test18(i64 %L) {
; CHECK-LABEL: test18:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: testq %rdi, %rdi # encoding: [0x48,0x85,0xff]
@@ -374,7 +374,7 @@ entry:
}
; This test failed due to incorrect handling of "shift + icmp" sequence
-define void @test20(i32 %bf.load, i8 %x1, i8* %b_addr) {
+define dso_local void @test20(i32 %bf.load, i8 %x1, i8* %b_addr) {
; CHECK-LABEL: test20:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0]
@@ -406,7 +406,7 @@ entry:
}
-define i32 @test21(i64 %val) {
+define dso_local i32 @test21(i64 %val) {
; CHECK-LABEL: test21:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0]
@@ -422,7 +422,7 @@ entry:
}
; AND-to-SHR transformation is enabled for eq/ne condition codes only.
-define i32 @test22(i64 %val) {
+define dso_local i32 @test22(i64 %val) {
; CHECK-LABEL: test22:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0]
@@ -435,7 +435,7 @@ entry:
}
-define i32 @test23(i64 %val) {
+define dso_local i32 @test23(i64 %val) {
; CHECK-LABEL: test23:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0]
@@ -451,7 +451,7 @@ entry:
}
-define i32 @test24(i64 %val) {
+define dso_local i32 @test24(i64 %val) {
; CHECK-LABEL: test24:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0]
@@ -486,7 +486,7 @@ define { i64, i64 } @pr39968(i64, i64, i32) {
; Make sure we use a 32-bit comparison without an extend based on the input
; being pre-sign extended by caller.
-define i32 @pr42189(i16 signext %c) {
+define dso_local i32 @pr42189(i16 signext %c) {
; CHECK-LABEL: pr42189:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: cmpl $32767, %edi # encoding: [0x81,0xff,0xff,0x7f,0x00,0x00]
diff --git a/llvm/test/CodeGen/X86/copy-eflags.ll b/llvm/test/CodeGen/X86/copy-eflags.ll
index 707faf939e55..5a232a92ada1 100644
--- a/llvm/test/CodeGen/X86/copy-eflags.ll
+++ b/llvm/test/CodeGen/X86/copy-eflags.ll
@@ -4,10 +4,10 @@
;
; Test patterns that require preserving and restoring flags.
- at b = common global i8 0, align 1
- at c = common global i32 0, align 4
- at a = common global i8 0, align 1
- at d = common global i8 0, align 1
+ at b = common dso_local global i8 0, align 1
+ at c = common dso_local global i32 0, align 4
+ at a = common dso_local global i8 0, align 1
+ at d = common dso_local global i8 0, align 1
@.str = private unnamed_addr constant [4 x i8] c"%d\0A\00", align 1
declare dso_local void @external(i32)
@@ -15,7 +15,7 @@ declare dso_local void @external(i32)
; A test that re-uses flags in interesting ways due to volatile accesses.
; Specifically, the first increment's flags are reused for the branch despite
; being clobbered by the second increment.
-define i32 @test1() nounwind {
+define dso_local i32 @test1() nounwind {
; X32-LABEL: test1:
; X32: # %bb.0: # %entry
; X32-NEXT: movb b, %cl
@@ -89,7 +89,7 @@ if.end:
}
; Preserve increment flags across a call.
-define i32 @test2(i32* %ptr) nounwind {
+define dso_local i32 @test2(i32* %ptr) nounwind {
; X32-LABEL: test2:
; X32: # %bb.0: # %entry
; X32-NEXT: pushl %ebx
@@ -150,7 +150,7 @@ declare dso_local void @external_b()
; use volatile stores similar to test1 to force the save and restore of
; a condition without calling another function. We then set up subsequent calls
; in tail position.
-define void @test_tail_call(i32* %ptr) nounwind optsize {
+define dso_local void @test_tail_call(i32* %ptr) nounwind optsize {
; X32-LABEL: test_tail_call:
; X32: # %bb.0: # %entry
; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
@@ -198,7 +198,7 @@ else:
; Test a function that gets special select lowering into CFG with copied EFLAGS
; threaded across the CFG. This requires our EFLAGS copy rewriting to handle
; cross-block rewrites in at least some narrow cases.
-define void @PR37100(i8 %arg1, i16 %arg2, i64 %arg3, i8 %arg4, i8* %ptr1, i32* %ptr2, i32 %x) nounwind {
+define dso_local void @PR37100(i8 %arg1, i16 %arg2, i64 %arg3, i8 %arg4, i8* %ptr1, i32* %ptr2, i32 %x) nounwind {
; X32-LABEL: PR37100:
; X32: # %bb.0: # %bb
; X32-NEXT: pushl %ebp
@@ -290,7 +290,7 @@ bb1:
; Use a particular instruction pattern in order to lower to the post-RA pseudo
; used to lower SETB into an SBB pattern in order to make sure that kind of
; usage of a copied EFLAGS continues to work.
-define void @PR37431(i32* %arg1, i8* %arg2, i8* %arg3, i32 %arg4, i64 %arg5) nounwind {
+define dso_local void @PR37431(i32* %arg1, i8* %arg2, i8* %arg3, i32 %arg4, i64 %arg5) nounwind {
; X32-LABEL: PR37431:
; X32: # %bb.0: # %entry
; X32-NEXT: pushl %ebx
diff --git a/llvm/test/CodeGen/X86/critical-edge-split-2.ll b/llvm/test/CodeGen/X86/critical-edge-split-2.ll
index 2eebed65f735..e8aa04d7dd8c 100644
--- a/llvm/test/CodeGen/X86/critical-edge-split-2.ll
+++ b/llvm/test/CodeGen/X86/critical-edge-split-2.ll
@@ -4,8 +4,8 @@
%0 = type <{ %1, %1 }>
%1 = type { i8, i8, i8, i8 }
- at g_2 = global %0 zeroinitializer
- at g_4 = global %1 zeroinitializer, align 4
+ at g_2 = dso_local global %0 zeroinitializer
+ at g_4 = dso_local global %1 zeroinitializer, align 4
; PR8642
define i16 @test1(i1 zeroext %C, i8** nocapture %argv) nounwind ssp {
diff --git a/llvm/test/CodeGen/X86/dbg-changes-codegen.ll b/llvm/test/CodeGen/X86/dbg-changes-codegen.ll
index c16dce12d090..dcf72bc12656 100644
--- a/llvm/test/CodeGen/X86/dbg-changes-codegen.ll
+++ b/llvm/test/CodeGen/X86/dbg-changes-codegen.ll
@@ -35,10 +35,10 @@
%struct.Wibble = type { i32 }
%struct.Flibble = type { i8 }
- at pfoo = global %struct.Foo* null, align 8
- at wibble1 = global %struct.Wibble* null, align 8
- at wibble2 = global %struct.Wibble* null, align 8
- at flibble = global %struct.Flibble zeroinitializer, align 1
+ at pfoo = dso_local global %struct.Foo* null, align 8
+ at wibble1 = dso_local global %struct.Wibble* null, align 8
+ at wibble2 = dso_local global %struct.Wibble* null, align 8
+ at flibble = dso_local global %struct.Flibble zeroinitializer, align 1
; Function Attrs: nounwind readonly uwtable
define zeroext i1 @_ZN3Foo3batEv(%struct.Foo* %this) #0 align 2 {
@@ -50,7 +50,7 @@ entry:
}
; Function Attrs: nounwind uwtable
-define void @_Z3bazv() #1 {
+define dso_local void @_Z3bazv() #1 {
entry:
%0 = load %struct.Wibble*, %struct.Wibble** @wibble1, align 8
tail call void @llvm.dbg.value(metadata %struct.Flibble* undef, i64 0, metadata !65, metadata !DIExpression()), !dbg !DILocation(scope: !1)
diff --git a/llvm/test/CodeGen/X86/emutls-pie.ll b/llvm/test/CodeGen/X86/emutls-pie.ll
index 1f1fe640016b..38f0c245bee6 100644
--- a/llvm/test/CodeGen/X86/emutls-pie.ll
+++ b/llvm/test/CodeGen/X86/emutls-pie.ll
@@ -22,7 +22,7 @@
@my_emutls_v_xyz = external global i8*, align 4
declare i8* @my_emutls_get_address(i8*)
-define i32 @my_get_xyz() {
+define dso_local i32 @my_get_xyz() {
; X86-LABEL: my_get_xyz:
; X86: movl my_emutls_v_xyz at GOT(%ebx), %eax
; X86-NEXT: movl %eax, (%esp)
@@ -48,10 +48,10 @@ entry:
ret i32 %1
}
- at i = thread_local global i32 15
+ at i = dso_local thread_local global i32 15
@i2 = external thread_local global i32
-define i32 @f1() {
+define dso_local i32 @f1() {
; X86-LABEL: f1:
; X86: leal __emutls_v.i at GOTOFF(%ebx), %eax
; X86-NEXT: movl %eax, (%esp)
@@ -75,7 +75,7 @@ entry:
ret i32 %tmp1
}
-define i32* @f2() {
+define dso_local i32* @f2() {
; X86-LABEL: f2:
; X86: leal __emutls_v.i at GOTOFF(%ebx), %eax
; X86-NEXT: movl %eax, (%esp)
@@ -88,7 +88,7 @@ entry:
ret i32* @i
}
-define i32 @f3() {
+define dso_local i32 @f3() {
; X86-LABEL: f3:
; X86: movl __emutls_v.i2 at GOT(%ebx), %eax
; X86-NEXT: movl %eax, (%esp)
@@ -102,7 +102,7 @@ entry:
ret i32 %tmp1
}
-define i32* @f4() {
+define dso_local i32* @f4() {
; X86-LABEL: f4:
; X86: movl __emutls_v.i2 at GOT(%ebx), %eax
; X86-NEXT: movl %eax, (%esp)
diff --git a/llvm/test/CodeGen/X86/emutls.ll b/llvm/test/CodeGen/X86/emutls.ll
index 77c4f88e5dac..7e567d287c61 100644
--- a/llvm/test/CodeGen/X86/emutls.ll
+++ b/llvm/test/CodeGen/X86/emutls.ll
@@ -17,7 +17,7 @@
@my_emutls_v_xyz = external global i8*, align 4
declare i8* @my_emutls_get_address(i8*)
-define i32 @my_get_xyz() {
+define dso_local i32 @my_get_xyz() {
; X86-LABEL: my_get_xyz:
; X86: movl $my_emutls_v_xyz, (%esp)
; X86-NEXT: calll my_emutls_get_address
@@ -40,15 +40,15 @@ entry:
ret i32 %1
}
- at i1 = thread_local global i32 15
+ at i1 = dso_local thread_local global i32 15
@i2 = external thread_local global i32
@i3 = internal thread_local global i32 15
@i4 = hidden thread_local global i32 15
@i5 = external hidden thread_local global i32
- at s1 = thread_local global i16 15
- at b1 = thread_local global i8 0
+ at s1 = dso_local thread_local global i16 15
+ at b1 = dso_local thread_local global i8 0
-define i32 @f1() {
+define dso_local i32 @f1() {
; X86-LABEL: f1:
; X86: movl $__emutls_v.i1, (%esp)
; X86-NEXT: calll __emutls_get_address
@@ -69,7 +69,7 @@ entry:
ret i32 %tmp1
}
-define i32* @f2() {
+define dso_local i32* @f2() {
; X86-LABEL: f2:
; X86: movl $__emutls_v.i1, (%esp)
; X86-NEXT: calll __emutls_get_address
@@ -87,7 +87,7 @@ entry:
ret i32* @i1
}
-define i32 @f3() nounwind {
+define dso_local i32 @f3() nounwind {
; X86-LABEL: f3:
; X86: movl $__emutls_v.i2, (%esp)
; X86-NEXT: calll __emutls_get_address
@@ -99,7 +99,7 @@ entry:
ret i32 %tmp1
}
-define i32* @f4() {
+define dso_local i32* @f4() {
; X86-LABEL: f4:
; X86: movl $__emutls_v.i2, (%esp)
; X86-NEXT: calll __emutls_get_address
@@ -110,7 +110,7 @@ entry:
ret i32* @i2
}
-define i32 @f5() nounwind {
+define dso_local i32 @f5() nounwind {
; X86-LABEL: f5:
; X86: movl $__emutls_v.i3, (%esp)
; X86-NEXT: calll __emutls_get_address
@@ -122,7 +122,7 @@ entry:
ret i32 %tmp1
}
-define i32* @f6() {
+define dso_local i32* @f6() {
; X86-LABEL: f6:
; X86: movl $__emutls_v.i3, (%esp)
; X86-NEXT: calll __emutls_get_address
@@ -133,7 +133,7 @@ entry:
ret i32* @i3
}
-define i32 @f7() {
+define dso_local i32 @f7() {
; X86-LABEL: f7:
; X86: movl $__emutls_v.i4, (%esp)
; X86-NEXT: calll __emutls_get_address
@@ -146,7 +146,7 @@ entry:
ret i32 %tmp1
}
-define i32* @f8() {
+define dso_local i32* @f8() {
; X86-LABEL: f8:
; X86: movl $__emutls_v.i4, (%esp)
; X86-NEXT: calll __emutls_get_address
@@ -157,7 +157,7 @@ entry:
ret i32* @i4
}
-define i32 @f9() {
+define dso_local i32 @f9() {
; X86-LABEL: f9:
; X86: movl $__emutls_v.i5, (%esp)
; X86-NEXT: calll __emutls_get_address
@@ -170,7 +170,7 @@ entry:
ret i32 %tmp1
}
-define i32* @f10() {
+define dso_local i32* @f10() {
; X86-LABEL: f10:
; X86: movl $__emutls_v.i5, (%esp)
; X86-NEXT: calll __emutls_get_address
@@ -181,7 +181,7 @@ entry:
ret i32* @i5
}
-define i16 @f11() {
+define dso_local i16 @f11() {
; X86-LABEL: f11:
; X86: movl $__emutls_v.s1, (%esp)
; X86-NEXT: calll __emutls_get_address
@@ -194,7 +194,7 @@ entry:
ret i16 %tmp1
}
-define i32 @f12() {
+define dso_local i32 @f12() {
; X86-LABEL: f12:
; X86: movl $__emutls_v.s1, (%esp)
; X86-NEXT: calll __emutls_get_address
@@ -208,7 +208,7 @@ entry:
ret i32 %tmp2
}
-define i8 @f13() {
+define dso_local i8 @f13() {
; X86-LABEL: f13:
; X86: movl $__emutls_v.b1, (%esp)
; X86-NEXT: calll __emutls_get_address
@@ -221,7 +221,7 @@ entry:
ret i8 %tmp1
}
-define i32 @f14() {
+define dso_local i32 @f14() {
; X86-LABEL: f14:
; X86: movl $__emutls_v.b1, (%esp)
; X86-NEXT: calll __emutls_get_address
diff --git a/llvm/test/CodeGen/X86/fmf-flags.ll b/llvm/test/CodeGen/X86/fmf-flags.ll
index 752e0c189c55..835ec72ff591 100644
--- a/llvm/test/CodeGen/X86/fmf-flags.ll
+++ b/llvm/test/CodeGen/X86/fmf-flags.ll
@@ -4,7 +4,7 @@
declare float @llvm.sqrt.f32(float %x);
-define float @fast_recip_sqrt(float %x) {
+define dso_local float @fast_recip_sqrt(float %x) {
; X64-LABEL: fast_recip_sqrt:
; X64: # %bb.0:
; X64-NEXT: rsqrtss %xmm0, %xmm1
@@ -29,7 +29,7 @@ define float @fast_recip_sqrt(float %x) {
declare float @llvm.fmuladd.f32(float %a, float %b, float %c);
-define float @fast_fmuladd_opts(float %a , float %b , float %c) {
+define dso_local float @fast_fmuladd_opts(float %a , float %b , float %c) {
; X64-LABEL: fast_fmuladd_opts:
; X64: # %bb.0:
; X64-NEXT: mulss {{.*}}(%rip), %xmm0
@@ -46,9 +46,9 @@ define float @fast_fmuladd_opts(float %a , float %b , float %c) {
; The multiply is strict.
- at mul1 = common global double 0.000000e+00, align 4
+ at mul1 = common dso_local global double 0.000000e+00, align 4
-define double @not_so_fast_mul_add(double %x) {
+define dso_local double @not_so_fast_mul_add(double %x) {
; X64-LABEL: not_so_fast_mul_add:
; X64: # %bb.0:
; X64-NEXT: movsd {{.*#+}} xmm1 = mem[0],zero
@@ -75,9 +75,9 @@ define double @not_so_fast_mul_add(double %x) {
; The sqrt is strict.
- at sqrt1 = common global float 0.000000e+00, align 4
+ at sqrt1 = common dso_local global float 0.000000e+00, align 4
-define float @not_so_fast_recip_sqrt(float %x) {
+define dso_local float @not_so_fast_recip_sqrt(float %x) {
; X64-LABEL: not_so_fast_recip_sqrt:
; X64: # %bb.0:
; X64-NEXT: rsqrtss %xmm0, %xmm1
@@ -106,7 +106,7 @@ define float @not_so_fast_recip_sqrt(float %x) {
ret float %z
}
-define float @div_arcp_by_const(half %x) {
+define dso_local float @div_arcp_by_const(half %x) {
; X64-LABEL: div_arcp_by_const:
; X64: # %bb.0:
; X64-NEXT: pushq %rax
diff --git a/llvm/test/CodeGen/X86/fp128-cast-strict.ll b/llvm/test/CodeGen/X86/fp128-cast-strict.ll
index ce5b09f8d411..b2458cd09d77 100644
--- a/llvm/test/CodeGen/X86/fp128-cast-strict.ll
+++ b/llvm/test/CodeGen/X86/fp128-cast-strict.ll
@@ -9,12 +9,12 @@
; Check soft floating point conversion function calls.
- at vf32 = common global float 0.000000e+00, align 4
- at vf64 = common global double 0.000000e+00, align 8
- at vf80 = common global x86_fp80 0xK00000000000000000000, align 8
- at vf128 = common global fp128 0xL00000000000000000000000000000000, align 16
+ at vf32 = common dso_local global float 0.000000e+00, align 4
+ at vf64 = common dso_local global double 0.000000e+00, align 8
+ at vf80 = common dso_local global x86_fp80 0xK00000000000000000000, align 8
+ at vf128 = common dso_local global fp128 0xL00000000000000000000000000000000, align 16
-define void @TestFPExtF32_F128() nounwind strictfp {
+define dso_local void @TestFPExtF32_F128() nounwind strictfp {
; X64-SSE-LABEL: TestFPExtF32_F128:
; X64-SSE: # %bb.0: # %entry
; X64-SSE-NEXT: pushq %rax
@@ -62,7 +62,7 @@ entry:
ret void
}
-define void @TestFPExtF64_F128() nounwind strictfp {
+define dso_local void @TestFPExtF64_F128() nounwind strictfp {
; X64-SSE-LABEL: TestFPExtF64_F128:
; X64-SSE: # %bb.0: # %entry
; X64-SSE-NEXT: pushq %rax
@@ -110,7 +110,7 @@ entry:
ret void
}
-define void @TestFPExtF80_F128() nounwind strictfp {
+define dso_local void @TestFPExtF80_F128() nounwind strictfp {
; X64-SSE-LABEL: TestFPExtF80_F128:
; X64-SSE: # %bb.0: # %entry
; X64-SSE-NEXT: subq $24, %rsp
@@ -162,7 +162,7 @@ entry:
ret void
}
-define void @TestFPTruncF128_F32() nounwind strictfp {
+define dso_local void @TestFPTruncF128_F32() nounwind strictfp {
; X64-SSE-LABEL: TestFPTruncF128_F32:
; X64-SSE: # %bb.0: # %entry
; X64-SSE-NEXT: pushq %rax
@@ -201,7 +201,7 @@ entry:
ret void
}
-define void @TestFPTruncF128_F64() nounwind strictfp {
+define dso_local void @TestFPTruncF128_F64() nounwind strictfp {
; X64-SSE-LABEL: TestFPTruncF128_F64:
; X64-SSE: # %bb.0: # %entry
; X64-SSE-NEXT: pushq %rax
@@ -240,7 +240,7 @@ entry:
ret void
}
-define void @TestFPTruncF128_F80() nounwind strictfp {
+define dso_local void @TestFPTruncF128_F80() nounwind strictfp {
; X64-SSE-LABEL: TestFPTruncF128_F80:
; X64-SSE: # %bb.0: # %entry
; X64-SSE-NEXT: pushq %rax
@@ -281,7 +281,7 @@ entry:
ret void
}
-define i8 @fptosi_i8(fp128 %x) nounwind strictfp {
+define dso_local i8 @fptosi_i8(fp128 %x) nounwind strictfp {
; X64-LABEL: fptosi_i8:
; X64: # %bb.0: # %entry
; X64-NEXT: pushq %rax
@@ -333,7 +333,7 @@ entry:
ret i16 %conv
}
-define i32 @fptosi_i32(fp128 %x) nounwind strictfp {
+define dso_local i32 @fptosi_i32(fp128 %x) nounwind strictfp {
; X64-LABEL: fptosi_i32:
; X64: # %bb.0: # %entry
; X64-NEXT: pushq %rax
@@ -420,7 +420,7 @@ entry:
ret i128 %conv
}
-define i8 @fptoui_i8(fp128 %x) nounwind strictfp {
+define dso_local i8 @fptoui_i8(fp128 %x) nounwind strictfp {
; X64-LABEL: fptoui_i8:
; X64: # %bb.0: # %entry
; X64-NEXT: pushq %rax
@@ -472,7 +472,7 @@ entry:
ret i16 %conv
}
-define i32 @fptoui_i32(fp128 %x) nounwind strictfp {
+define dso_local i32 @fptoui_i32(fp128 %x) nounwind strictfp {
; X64-LABEL: fptoui_i32:
; X64: # %bb.0: # %entry
; X64-NEXT: pushq %rax
diff --git a/llvm/test/CodeGen/X86/fp128-cast.ll b/llvm/test/CodeGen/X86/fp128-cast.ll
index 3db1901d0e14..6093095d51d0 100644
--- a/llvm/test/CodeGen/X86/fp128-cast.ll
+++ b/llvm/test/CodeGen/X86/fp128-cast.ll
@@ -9,19 +9,19 @@
; Check soft floating point conversion function calls.
- at vi16 = common global i16 0, align 2
- at vi32 = common global i32 0, align 4
- at vi64 = common global i64 0, align 8
- at vi128 = common global i128 0, align 16
- at vu32 = common global i32 0, align 4
- at vu64 = common global i64 0, align 8
- at vu128 = common global i128 0, align 16
- at vf32 = common global float 0.000000e+00, align 4
- at vf64 = common global double 0.000000e+00, align 8
- at vf80 = common global x86_fp80 0xK00000000000000000000, align 8
- at vf128 = common global fp128 0xL00000000000000000000000000000000, align 16
+ at vi16 = common dso_local global i16 0, align 2
+ at vi32 = common dso_local global i32 0, align 4
+ at vi64 = common dso_local global i64 0, align 8
+ at vi128 = common dso_local global i128 0, align 16
+ at vu32 = common dso_local global i32 0, align 4
+ at vu64 = common dso_local global i64 0, align 8
+ at vu128 = common dso_local global i128 0, align 16
+ at vf32 = common dso_local global float 0.000000e+00, align 4
+ at vf64 = common dso_local global double 0.000000e+00, align 8
+ at vf80 = common dso_local global x86_fp80 0xK00000000000000000000, align 8
+ at vf128 = common dso_local global fp128 0xL00000000000000000000000000000000, align 16
-define void @TestFPExtF32_F128() nounwind {
+define dso_local void @TestFPExtF32_F128() nounwind {
; X64-SSE-LABEL: TestFPExtF32_F128:
; X64-SSE: # %bb.0: # %entry
; X64-SSE-NEXT: pushq %rax
@@ -68,7 +68,7 @@ entry:
ret void
}
-define void @TestFPExtF64_F128() nounwind {
+define dso_local void @TestFPExtF64_F128() nounwind {
; X64-SSE-LABEL: TestFPExtF64_F128:
; X64-SSE: # %bb.0: # %entry
; X64-SSE-NEXT: pushq %rax
@@ -115,7 +115,7 @@ entry:
ret void
}
-define void @TestFPExtF80_F128() nounwind {
+define dso_local void @TestFPExtF80_F128() nounwind {
; X64-SSE-LABEL: TestFPExtF80_F128:
; X64-SSE: # %bb.0: # %entry
; X64-SSE-NEXT: subq $24, %rsp
@@ -164,7 +164,7 @@ entry:
ret void
}
-define void @TestFPToSIF128_I16() nounwind {
+define dso_local void @TestFPToSIF128_I16() nounwind {
; X64-SSE-LABEL: TestFPToSIF128_I16:
; X64-SSE: # %bb.0: # %entry
; X64-SSE-NEXT: pushq %rax
@@ -202,7 +202,7 @@ entry:
ret void
}
-define void @TestFPToUIF128_I16() nounwind {
+define dso_local void @TestFPToUIF128_I16() nounwind {
; X64-SSE-LABEL: TestFPToUIF128_I16:
; X64-SSE: # %bb.0: # %entry
; X64-SSE-NEXT: pushq %rax
@@ -240,7 +240,7 @@ entry:
ret void
}
-define void @TestFPToSIF128_I32() nounwind {
+define dso_local void @TestFPToSIF128_I32() nounwind {
; X64-SSE-LABEL: TestFPToSIF128_I32:
; X64-SSE: # %bb.0: # %entry
; X64-SSE-NEXT: pushq %rax
@@ -278,7 +278,7 @@ entry:
ret void
}
-define void @TestFPToUIF128_U32() nounwind {
+define dso_local void @TestFPToUIF128_U32() nounwind {
; X64-SSE-LABEL: TestFPToUIF128_U32:
; X64-SSE: # %bb.0: # %entry
; X64-SSE-NEXT: pushq %rax
@@ -316,7 +316,7 @@ entry:
ret void
}
-define void @TestFPToSIF128_I64() nounwind {
+define dso_local void @TestFPToSIF128_I64() nounwind {
; X64-SSE-LABEL: TestFPToSIF128_I64:
; X64-SSE: # %bb.0: # %entry
; X64-SSE-NEXT: pushq %rax
@@ -359,7 +359,7 @@ entry:
ret void
}
-define void @TestFPToUIF128_U64() nounwind {
+define dso_local void @TestFPToUIF128_U64() nounwind {
; X64-SSE-LABEL: TestFPToUIF128_U64:
; X64-SSE: # %bb.0: # %entry
; X64-SSE-NEXT: pushq %rax
@@ -401,7 +401,7 @@ entry:
ret void
}
-define void @TestFPToSIF128_I128() nounwind {
+define dso_local void @TestFPToSIF128_I128() nounwind {
; X64-SSE-LABEL: TestFPToSIF128_I128:
; X64-SSE: # %bb.0: # %entry
; X64-SSE-NEXT: pushq %rax
@@ -452,7 +452,7 @@ entry:
ret void
}
-define void @TestFPToUIF128_U128() nounwind {
+define dso_local void @TestFPToUIF128_U128() nounwind {
; X64-SSE-LABEL: TestFPToUIF128_U128:
; X64-SSE: # %bb.0: # %entry
; X64-SSE-NEXT: pushq %rax
@@ -503,7 +503,7 @@ entry:
ret void
}
-define void @TestFPTruncF128_F32() nounwind {
+define dso_local void @TestFPTruncF128_F32() nounwind {
; X64-SSE-LABEL: TestFPTruncF128_F32:
; X64-SSE: # %bb.0: # %entry
; X64-SSE-NEXT: pushq %rax
@@ -541,7 +541,7 @@ entry:
ret void
}
-define void @TestFPTruncF128_F64() nounwind {
+define dso_local void @TestFPTruncF128_F64() nounwind {
; X64-SSE-LABEL: TestFPTruncF128_F64:
; X64-SSE: # %bb.0: # %entry
; X64-SSE-NEXT: pushq %rax
@@ -579,7 +579,7 @@ entry:
ret void
}
-define void @TestFPTruncF128_F80() nounwind {
+define dso_local void @TestFPTruncF128_F80() nounwind {
; X64-SSE-LABEL: TestFPTruncF128_F80:
; X64-SSE: # %bb.0: # %entry
; X64-SSE-NEXT: pushq %rax
@@ -617,7 +617,7 @@ entry:
ret void
}
-define void @TestSIToFPI16_F128() nounwind {
+define dso_local void @TestSIToFPI16_F128() nounwind {
; X64-SSE-LABEL: TestSIToFPI16_F128:
; X64-SSE: # %bb.0: # %entry
; X64-SSE-NEXT: pushq %rax
@@ -665,7 +665,7 @@ entry:
ret void
}
-define void @TestSIToFPU16_F128() nounwind {
+define dso_local void @TestSIToFPU16_F128() nounwind {
; X64-SSE-LABEL: TestSIToFPU16_F128:
; X64-SSE: # %bb.0: # %entry
; X64-SSE-NEXT: pushq %rax
@@ -713,7 +713,7 @@ entry:
ret void
}
-define void @TestSIToFPI32_F128() nounwind {
+define dso_local void @TestSIToFPI32_F128() nounwind {
; X64-SSE-LABEL: TestSIToFPI32_F128:
; X64-SSE: # %bb.0: # %entry
; X64-SSE-NEXT: pushq %rax
@@ -759,7 +759,7 @@ entry:
ret void
}
-define void @TestUIToFPU32_F128() #2 {
+define dso_local void @TestUIToFPU32_F128() #2 {
; X64-SSE-LABEL: TestUIToFPU32_F128:
; X64-SSE: # %bb.0: # %entry
; X64-SSE-NEXT: pushq %rax
@@ -805,7 +805,7 @@ entry:
ret void
}
-define void @TestSIToFPI64_F128() nounwind {
+define dso_local void @TestSIToFPI64_F128() nounwind {
; X64-SSE-LABEL: TestSIToFPI64_F128:
; X64-SSE: # %bb.0: # %entry
; X64-SSE-NEXT: pushq %rax
@@ -852,7 +852,7 @@ entry:
ret void
}
-define void @TestUIToFPU64_F128() #2 {
+define dso_local void @TestUIToFPU64_F128() #2 {
; X64-SSE-LABEL: TestUIToFPU64_F128:
; X64-SSE: # %bb.0: # %entry
; X64-SSE-NEXT: pushq %rax
@@ -899,7 +899,7 @@ entry:
ret void
}
-define void @TestSIToFPI128_F128() nounwind {
+define dso_local void @TestSIToFPI128_F128() nounwind {
; X64-SSE-LABEL: TestSIToFPI128_F128:
; X64-SSE: # %bb.0: # %entry
; X64-SSE-NEXT: pushq %rax
@@ -950,7 +950,7 @@ entry:
ret void
}
-define void @TestUIToFPU128_F128() #2 {
+define dso_local void @TestUIToFPU128_F128() #2 {
; X64-SSE-LABEL: TestUIToFPU128_F128:
; X64-SSE: # %bb.0: # %entry
; X64-SSE-NEXT: pushq %rax
@@ -1001,7 +1001,7 @@ entry:
ret void
}
-define i32 @TestConst128(fp128 %v) nounwind {
+define dso_local i32 @TestConst128(fp128 %v) nounwind {
; X64-SSE-LABEL: TestConst128:
; X64-SSE: # %bb.0: # %entry
; X64-SSE-NEXT: pushq %rax
@@ -1052,7 +1052,7 @@ entry:
}
-define i32 @TestConst128Zero(fp128 %v) nounwind {
+define dso_local i32 @TestConst128Zero(fp128 %v) nounwind {
; X64-SSE-LABEL: TestConst128Zero:
; X64-SSE: # %bb.0: # %entry
; X64-SSE-NEXT: pushq %rax
@@ -1116,7 +1116,7 @@ entry:
; u.ld = ld * ld;
; return ((u.bits.v1 | u.bits.v2) == 0);
; }
-define i32 @TestBits128(fp128 %ld) nounwind {
+define dso_local i32 @TestBits128(fp128 %ld) nounwind {
; X64-SSE-LABEL: TestBits128:
; X64-SSE: # %bb.0: # %entry
; X64-SSE-NEXT: subq $24, %rsp
diff --git a/llvm/test/CodeGen/X86/fp128-g.ll b/llvm/test/CodeGen/X86/fp128-g.ll
index 8130e0bd118e..c52d7bfda3e3 100644
--- a/llvm/test/CodeGen/X86/fp128-g.ll
+++ b/llvm/test/CodeGen/X86/fp128-g.ll
@@ -12,7 +12,7 @@ source_filename = "fp128-g.c"
target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
target triple = "x86_64--linux-android"
- at ld_ptr = common local_unnamed_addr global fp128* null, align 8, !dbg !0
+ at ld_ptr = common dso_local local_unnamed_addr global fp128* null, align 8, !dbg !0
; Function Attrs: nounwind readonly uwtable
define fp128 @test_return1(fp128* nocapture readonly %ptr) local_unnamed_addr #0 !dbg !12 {
diff --git a/llvm/test/CodeGen/X86/fp128-i128.ll b/llvm/test/CodeGen/X86/fp128-i128.ll
index 58af70d5d0b1..90224de50338 100644
--- a/llvm/test/CodeGen/X86/fp128-i128.ll
+++ b/llvm/test/CodeGen/X86/fp128-i128.ll
@@ -45,7 +45,7 @@
; w = u.e;
; foo(w);
; }
-define void @TestUnionLD1(fp128 %s, i64 %n) #0 {
+define dso_local void @TestUnionLD1(fp128 %s, i64 %n) #0 {
; SSE-LABEL: TestUnionLD1:
; SSE: # %bb.0: # %entry
; SSE-NEXT: movaps %xmm0, -{{[0-9]+}}(%rsp)
@@ -334,15 +334,15 @@ entry:
ret fp128 %add
}
- at v128 = common global i128 0, align 16
- at v128_2 = common global i128 0, align 16
+ at v128 = common dso_local global i128 0, align 16
+ at v128_2 = common dso_local global i128 0, align 16
; C code:
; unsigned __int128 v128, v128_2;
; void TestShift128_2() {
; v128 = ((v128 << 96) | v128_2);
; }
-define void @TestShift128_2() #2 {
+define dso_local void @TestShift128_2() #2 {
; CHECK-LABEL: TestShift128_2:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: movq {{.*}}(%rip), %rax
@@ -440,7 +440,7 @@ declare fp128 @fabsl(fp128) #1
declare fp128 @copysignl(fp128, fp128) #1
; Test more complicated logical operations generated from copysignl.
-define void @TestCopySign({ fp128, fp128 }* noalias nocapture sret({ fp128, fp128 }) %agg.result, { fp128, fp128 }* byval({ fp128, fp128 }) nocapture readonly align 16 %z) #0 {
+define dso_local void @TestCopySign({ fp128, fp128 }* noalias nocapture sret({ fp128, fp128 }) %agg.result, { fp128, fp128 }* byval({ fp128, fp128 }) nocapture readonly align 16 %z) #0 {
; SSE-LABEL: TestCopySign:
; SSE: # %bb.0: # %entry
; SSE-NEXT: pushq %rbp
diff --git a/llvm/test/CodeGen/X86/fp128-libcalls.ll b/llvm/test/CodeGen/X86/fp128-libcalls.ll
index fad69fc7a25d..a16a99288eb9 100644
--- a/llvm/test/CodeGen/X86/fp128-libcalls.ll
+++ b/llvm/test/CodeGen/X86/fp128-libcalls.ll
@@ -8,10 +8,10 @@
; Check all soft floating point library function calls.
- at vf64 = common global double 0.000000e+00, align 8
- at vf128 = common global fp128 0xL00000000000000000000000000000000, align 16
+ at vf64 = common dso_local global double 0.000000e+00, align 8
+ at vf128 = common dso_local global fp128 0xL00000000000000000000000000000000, align 16
-define void @Test128Add(fp128 %d1, fp128 %d2) nounwind {
+define dso_local void @Test128Add(fp128 %d1, fp128 %d2) nounwind {
; CHECK-LABEL: Test128Add:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: pushq %rax
@@ -53,7 +53,7 @@ entry:
ret void
}
-define void @Test128_1Add(fp128 %d1) nounwind {
+define dso_local void @Test128_1Add(fp128 %d1) nounwind {
; CHECK-LABEL: Test128_1Add:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: pushq %rax
@@ -98,7 +98,7 @@ entry:
ret void
}
-define void @Test128Sub(fp128 %d1, fp128 %d2) nounwind {
+define dso_local void @Test128Sub(fp128 %d1, fp128 %d2) nounwind {
; CHECK-LABEL: Test128Sub:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: pushq %rax
@@ -140,7 +140,7 @@ entry:
ret void
}
-define void @Test128_1Sub(fp128 %d1) nounwind {
+define dso_local void @Test128_1Sub(fp128 %d1) nounwind {
; CHECK-LABEL: Test128_1Sub:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: pushq %rax
@@ -185,7 +185,7 @@ entry:
ret void
}
-define void @Test128Mul(fp128 %d1, fp128 %d2) nounwind {
+define dso_local void @Test128Mul(fp128 %d1, fp128 %d2) nounwind {
; CHECK-LABEL: Test128Mul:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: pushq %rax
@@ -227,7 +227,7 @@ entry:
ret void
}
-define void @Test128_1Mul(fp128 %d1) nounwind {
+define dso_local void @Test128_1Mul(fp128 %d1) nounwind {
; CHECK-LABEL: Test128_1Mul:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: pushq %rax
@@ -272,7 +272,7 @@ entry:
ret void
}
-define void @Test128Div(fp128 %d1, fp128 %d2) nounwind {
+define dso_local void @Test128Div(fp128 %d1, fp128 %d2) nounwind {
; CHECK-LABEL: Test128Div:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: pushq %rax
@@ -314,7 +314,7 @@ entry:
ret void
}
-define void @Test128_1Div(fp128 %d1) nounwind {
+define dso_local void @Test128_1Div(fp128 %d1) nounwind {
; CHECK-LABEL: Test128_1Div:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: pushq %rax
@@ -359,7 +359,7 @@ entry:
ret void
}
-define void @Test128Rem(fp128 %d1, fp128 %d2) nounwind {
+define dso_local void @Test128Rem(fp128 %d1, fp128 %d2) nounwind {
; CHECK-LABEL: Test128Rem:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: pushq %rax
@@ -401,7 +401,7 @@ entry:
ret void
}
-define void @Test128_1Rem(fp128 %d1) nounwind {
+define dso_local void @Test128_1Rem(fp128 %d1) nounwind {
; CHECK-LABEL: Test128_1Rem:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: pushq %rax
@@ -446,7 +446,7 @@ entry:
ret void
}
-define void @Test128Sqrt(fp128 %d1) nounwind {
+define dso_local void @Test128Sqrt(fp128 %d1) nounwind {
; CHECK-LABEL: Test128Sqrt:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: pushq %rax
@@ -485,7 +485,7 @@ entry:
}
declare fp128 @llvm.sqrt.f128(fp128)
-define void @Test128Sin(fp128 %d1) nounwind {
+define dso_local void @Test128Sin(fp128 %d1) nounwind {
; CHECK-LABEL: Test128Sin:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: pushq %rax
@@ -524,7 +524,7 @@ entry:
}
declare fp128 @llvm.sin.f128(fp128)
-define void @Test128Cos(fp128 %d1) nounwind {
+define dso_local void @Test128Cos(fp128 %d1) nounwind {
; CHECK-LABEL: Test128Cos:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: pushq %rax
@@ -563,7 +563,7 @@ entry:
}
declare fp128 @llvm.cos.f128(fp128)
-define void @Test128Ceil(fp128 %d1) nounwind {
+define dso_local void @Test128Ceil(fp128 %d1) nounwind {
; CHECK-LABEL: Test128Ceil:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: pushq %rax
@@ -602,7 +602,7 @@ entry:
}
declare fp128 @llvm.ceil.f128(fp128)
-define void @Test128Floor(fp128 %d1) nounwind {
+define dso_local void @Test128Floor(fp128 %d1) nounwind {
; CHECK-LABEL: Test128Floor:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: pushq %rax
@@ -641,7 +641,7 @@ entry:
}
declare fp128 @llvm.floor.f128(fp128)
-define void @Test128Trunc(fp128 %d1) nounwind {
+define dso_local void @Test128Trunc(fp128 %d1) nounwind {
; CHECK-LABEL: Test128Trunc:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: pushq %rax
@@ -680,7 +680,7 @@ entry:
}
declare fp128 @llvm.trunc.f128(fp128)
-define void @Test128Nearbyint(fp128 %d1) nounwind {
+define dso_local void @Test128Nearbyint(fp128 %d1) nounwind {
; CHECK-LABEL: Test128Nearbyint:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: pushq %rax
@@ -719,7 +719,7 @@ entry:
}
declare fp128 @llvm.nearbyint.f128(fp128)
-define void @Test128Rint(fp128 %d1) nounwind {
+define dso_local void @Test128Rint(fp128 %d1) nounwind {
; CHECK-LABEL: Test128Rint:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: pushq %rax
@@ -758,7 +758,7 @@ entry:
}
declare fp128 @llvm.rint.f128(fp128)
-define void @Test128Round(fp128 %d1) nounwind {
+define dso_local void @Test128Round(fp128 %d1) nounwind {
; CHECK-LABEL: Test128Round:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: pushq %rax
diff --git a/llvm/test/CodeGen/X86/fp128-load.ll b/llvm/test/CodeGen/X86/fp128-load.ll
index 65a3ecf09067..913f2a48c760 100644
--- a/llvm/test/CodeGen/X86/fp128-load.ll
+++ b/llvm/test/CodeGen/X86/fp128-load.ll
@@ -5,7 +5,7 @@
; RUN: -enable-legalize-types-checking | FileCheck %s
; __float128 myFP128 = 1.0L; // x86_64-linux-android
- at my_fp128 = global fp128 0xL00000000000000003FFF000000000000, align 16
+ at my_fp128 = dso_local global fp128 0xL00000000000000003FFF000000000000, align 16
define fp128 @get_fp128() {
; CHECK-LABEL: get_fp128:
diff --git a/llvm/test/CodeGen/X86/fp128-store.ll b/llvm/test/CodeGen/X86/fp128-store.ll
index ca3af637cff5..789ff6afbcfb 100644
--- a/llvm/test/CodeGen/X86/fp128-store.ll
+++ b/llvm/test/CodeGen/X86/fp128-store.ll
@@ -2,9 +2,9 @@
; RUN: llc < %s -O2 -mtriple=x86_64-linux-gnu -mattr=+mmx | FileCheck %s
; __float128 myFP128 = 1.0L; // x86_64-linux-android
- at myFP128 = global fp128 0xL00000000000000003FFF000000000000, align 16
+ at myFP128 = dso_local global fp128 0xL00000000000000003FFF000000000000, align 16
-define void @set_FP128(fp128 %x) {
+define dso_local void @set_FP128(fp128 %x) {
entry:
store fp128 %x, fp128* @myFP128, align 16
ret void
diff --git a/llvm/test/CodeGen/X86/ga-offset.ll b/llvm/test/CodeGen/X86/ga-offset.ll
index 3613cf8bf598..c67ce2eaa1e9 100644
--- a/llvm/test/CodeGen/X86/ga-offset.ll
+++ b/llvm/test/CodeGen/X86/ga-offset.ll
@@ -1,9 +1,9 @@
; RUN: llc < %s -mtriple=x86_64-linux -relocation-model=static | FileCheck %s
- at ptr = global i32* null
- at dst = global [131072 x i32] zeroinitializer
+ at ptr = dso_local global i32* null
+ at dst = dso_local global [131072 x i32] zeroinitializer
-define void @foo() nounwind {
+define dso_local void @foo() nounwind {
; This store should fold to a single mov instruction.
; CHECK: movq $dst+64, ptr(%rip)
store i32* getelementptr ([131072 x i32], [131072 x i32]* @dst, i32 0, i32 16), i32** @ptr
diff --git a/llvm/test/CodeGen/X86/global-access-pie.ll b/llvm/test/CodeGen/X86/global-access-pie.ll
index d074f9fab8b2..b3bd4db5e3df 100644
--- a/llvm/test/CodeGen/X86/global-access-pie.ll
+++ b/llvm/test/CodeGen/X86/global-access-pie.ll
@@ -9,9 +9,9 @@
; RUN: | FileCheck -check-prefix=X32 %s
; External Linkage
- at a = global i32 0, align 4
+ at a = dso_local global i32 0, align 4
-define i32 @my_access_global_a() #0 {
+define dso_local i32 @my_access_global_a() #0 {
; X32-LABEL: my_access_global_a:
; X32: addl $_GLOBAL_OFFSET_TABLE_{{.*}}, %eax
; X32-NEXT: movl a at GOTOFF(%eax), %eax
@@ -24,9 +24,9 @@ entry:
}
; WeakAny Linkage
- at b = weak global i32 0, align 4
+ at b = weak dso_local global i32 0, align 4
-define i32 @my_access_global_b() #0 {
+define dso_local i32 @my_access_global_b() #0 {
; X32-LABEL: my_access_global_b:
; X32: addl $_GLOBAL_OFFSET_TABLE_{{.*}}, %eax
; X32-NEXT: movl b at GOTOFF(%eax), %eax
@@ -41,7 +41,7 @@ entry:
; Internal Linkage
@c = internal global i32 0, align 4
-define i32 @my_access_global_c() #0 {
+define dso_local i32 @my_access_global_c() #0 {
; X32-LABEL: my_access_global_c:
; X32: addl $_GLOBAL_OFFSET_TABLE_{{.*}}, %eax
; X32-NEXT: movl c at GOTOFF(%eax), %eax
@@ -56,7 +56,7 @@ entry:
; External Linkage, only declaration.
@d = external global i32, align 4
-define i32 @my_access_global_load_d() #0 {
+define dso_local i32 @my_access_global_load_d() #0 {
; X32-LABEL: my_access_global_load_d:
; X32: addl $_GLOBAL_OFFSET_TABLE_{{.*}}, %eax
; X32-NEXT: movl d at GOT(%eax), %eax
@@ -72,7 +72,7 @@ entry:
; External Linkage, only declaration, store a value.
-define i32 @my_access_global_store_d() #0 {
+define dso_local i32 @my_access_global_store_d() #0 {
; X32-LABEL: my_access_global_store_d:
; X32: addl $_GLOBAL_OFFSET_TABLE_{{.*}}, %eax
; X32-NEXT: movl d at GOT(%eax), %eax
@@ -90,7 +90,7 @@ entry:
declare i32 @access_fp(i32 ()*)
declare i32 @foo()
-define i32 @my_access_fp_foo() #0 {
+define dso_local i32 @my_access_fp_foo() #0 {
; X32-LABEL: my_access_fp_foo:
; X32: addl $_GLOBAL_OFFSET_TABLE_{{.*}}, %ebx
; X32-NEXT: movl foo at GOT(%ebx), %eax
@@ -106,15 +106,15 @@ entry:
$bar = comdat any
-define linkonce_odr i32 @bar() comdat {
+define linkonce_odr dso_local i32 @bar() comdat {
entry:
ret i32 0
}
-define i32 @my_access_fp_bar() #0 {
+define dso_local i32 @my_access_fp_bar() #0 {
; X32-LABEL: my_access_fp_bar:
; X32: addl $_GLOBAL_OFFSET_TABLE_{{.*}}, %ebx
-; X32-NEXT: leal bar at GOTOFF(%ebx), %eax
+; X32-NEXT: leal bar at GOTOFF(%ebx), %eax
; X64-LABEL: my_access_fp_bar:
; X64: leaq bar(%rip), %rdi
diff --git a/llvm/test/CodeGen/X86/hoist-spill-lpad.ll b/llvm/test/CodeGen/X86/hoist-spill-lpad.ll
index 3171f6f9f6fd..5991554552af 100644
--- a/llvm/test/CodeGen/X86/hoist-spill-lpad.ll
+++ b/llvm/test/CodeGen/X86/hoist-spill-lpad.ll
@@ -12,11 +12,11 @@
target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"
- at a = global [20 x i64] zeroinitializer, align 16
+ at a = dso_local global [20 x i64] zeroinitializer, align 16
@_ZTIi = external constant i8*
; Function Attrs: uwtable
-define void @_Z3foov() personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) {
+define dso_local void @_Z3foov() personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) {
entry:
%tmp = load i64, i64* getelementptr inbounds ([20 x i64], [20 x i64]* @a, i64 0, i64 1), align 8
invoke void @_Z3goov()
diff --git a/llvm/test/CodeGen/X86/immediate_merging.ll b/llvm/test/CodeGen/X86/immediate_merging.ll
index 038c56f6dd5d..49cf4c5949d8 100644
--- a/llvm/test/CodeGen/X86/immediate_merging.ll
+++ b/llvm/test/CodeGen/X86/immediate_merging.ll
@@ -2,19 +2,19 @@
; RUN: llc < %s -mtriple=i386-unknown-linux-gnu | FileCheck %s --check-prefix=X86
; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu | FileCheck %s --check-prefix=X64
- at a = common global i32 0, align 4
- at b = common global i32 0, align 4
- at c = common global i32 0, align 4
- at e = common global i32 0, align 4
- at x = common global i32 0, align 4
- at f = common global i32 0, align 4
- at h = common global i32 0, align 4
- at i = common global i32 0, align 4
+ at a = common dso_local global i32 0, align 4
+ at b = common dso_local global i32 0, align 4
+ at c = common dso_local global i32 0, align 4
+ at e = common dso_local global i32 0, align 4
+ at x = common dso_local global i32 0, align 4
+ at f = common dso_local global i32 0, align 4
+ at h = common dso_local global i32 0, align 4
+ at i = common dso_local global i32 0, align 4
; Test -Os to make sure immediates with multiple users don't get pulled in to
; instructions (8-bit immediates are exceptions).
-define i32 @foo() optsize {
+define dso_local i32 @foo() optsize {
; X86-LABEL: foo:
; X86: # %bb.0: # %entry
; X86-NEXT: movl $1234, %eax # imm = 0x4D2
@@ -75,7 +75,7 @@ if.end: ; preds = %if.then, %entry
; Test PGSO to make sure immediates with multiple users don't get pulled in to
; instructions (8-bit immediates are exceptions).
-define i32 @foo_pgso() !prof !14 {
+define dso_local i32 @foo_pgso() !prof !14 {
; X86-LABEL: foo_pgso:
; X86: # %bb.0: # %entry
; X86-NEXT: movl $1234, %eax # imm = 0x4D2
@@ -134,7 +134,7 @@ if.end: ; preds = %if.then, %entry
}
; Test -O2 to make sure that all immediates get pulled in to their users.
-define i32 @foo2() {
+define dso_local i32 @foo2() {
; X86-LABEL: foo2:
; X86: # %bb.0: # %entry
; X86-NEXT: movl $1234, a # imm = 0x4D2
@@ -156,12 +156,12 @@ entry:
declare void @llvm.memset.p0i8.i32(i8* nocapture, i8, i32, i1) #1
- at AA = common global [100 x i8] zeroinitializer, align 1
+ at AA = common dso_local global [100 x i8] zeroinitializer, align 1
; memset gets lowered in DAG. Constant merging should hoist all the
; immediates used to store to the individual memory locations. Make
; sure we don't directly store the immediates.
-define void @foomemset() optsize {
+define dso_local void @foomemset() optsize {
; X86-LABEL: foomemset:
; X86: # %bb.0: # %entry
; X86-NEXT: movl $555819297, %eax # imm = 0x21212121
@@ -188,7 +188,7 @@ entry:
; memset gets lowered in DAG. Constant merging should hoist all the
; immediates used to store to the individual memory locations. Make
; sure we don't directly store the immediates.
-define void @foomemset_pgso() !prof !14 {
+define dso_local void @foomemset_pgso() !prof !14 {
; X86-LABEL: foomemset_pgso:
; X86: # %bb.0: # %entry
; X86-NEXT: movl $555819297, %eax # imm = 0x21212121
diff --git a/llvm/test/CodeGen/X86/inline-asm-h.ll b/llvm/test/CodeGen/X86/inline-asm-h.ll
index 8c3e45aba903..afb0be8765c5 100644
--- a/llvm/test/CodeGen/X86/inline-asm-h.ll
+++ b/llvm/test/CodeGen/X86/inline-asm-h.ll
@@ -1,8 +1,8 @@
; RUN: llc -mtriple=x86_64-pc-linux-gnu < %s | FileCheck %s
- at foobar = common global i32 0, align 4
+ at foobar = common dso_local global i32 0, align 4
-define void @zed() nounwind {
+define dso_local void @zed() nounwind {
entry:
call void asm "movq %mm2,${0:H}", "=*m,~{dirflag},~{fpsr},~{flags}"(i32* @foobar) nounwind
ret void
diff --git a/llvm/test/CodeGen/X86/lea-recursion.ll b/llvm/test/CodeGen/X86/lea-recursion.ll
index 9bc50f60cd89..bdd7b73e2d00 100644
--- a/llvm/test/CodeGen/X86/lea-recursion.ll
+++ b/llvm/test/CodeGen/X86/lea-recursion.ll
@@ -9,10 +9,10 @@
; fixed, the test commands above will need to be updated to expect fewer
; lea instructions.
- at g0 = weak global [1000 x i32] zeroinitializer, align 32 ; <[1000 x i32]*> [#uses=8]
- at g1 = weak global [1000 x i32] zeroinitializer, align 32 ; <[1000 x i32]*> [#uses=7]
+ at g0 = weak dso_local global [1000 x i32] zeroinitializer, align 32 ; <[1000 x i32]*> [#uses=8]
+ at g1 = weak dso_local global [1000 x i32] zeroinitializer, align 32 ; <[1000 x i32]*> [#uses=7]
-define void @foo() {
+define dso_local void @foo() {
; CHECK-LABEL: foo:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: movl {{.*}}(%rip), %eax
diff --git a/llvm/test/CodeGen/X86/linux-preemption.ll b/llvm/test/CodeGen/X86/linux-preemption.ll
index 4739e6cec011..326c00bc8d5f 100644
--- a/llvm/test/CodeGen/X86/linux-preemption.ll
+++ b/llvm/test/CodeGen/X86/linux-preemption.ll
@@ -12,8 +12,8 @@
; globals
- at strong_default_global = global i32 42
-define i32* @get_strong_default_global() {
+ at strong_default_global = dso_local global i32 42
+define dso_local i32* @get_strong_default_global() {
ret i32* @strong_default_global
}
; CHECK: movq strong_default_global at GOTPCREL(%rip), %rax
@@ -21,15 +21,15 @@ define i32* @get_strong_default_global() {
; CHECK32: movl strong_default_global at GOT(%eax), %eax
@strong_hidden_global = hidden global i32 42
-define i32* @get_hidden_default_global() {
+define dso_local i32* @get_hidden_default_global() {
ret i32* @strong_hidden_global
}
; CHECK: leaq strong_hidden_global(%rip), %rax
; STATIC: movl $strong_hidden_global, %eax
; CHECK32: leal strong_hidden_global at GOTOFF(%eax), %eax
- at weak_default_global = weak global i32 42
-define i32* @get_weak_default_global() {
+ at weak_default_global = weak dso_local global i32 42
+define dso_local i32* @get_weak_default_global() {
ret i32* @weak_default_global
}
; CHECK: movq weak_default_global at GOTPCREL(%rip), %rax
@@ -37,7 +37,7 @@ define i32* @get_weak_default_global() {
; CHECK32: movl weak_default_global at GOT(%eax), %eax
@external_default_global = external global i32
-define i32* @get_external_default_global() {
+define dso_local i32* @get_external_default_global() {
ret i32* @external_default_global
}
; CHECK: movq external_default_global at GOTPCREL(%rip), %rax
@@ -45,7 +45,7 @@ define i32* @get_external_default_global() {
; CHECK32: movl external_default_global at GOT(%eax), %eax
@strong_local_global = dso_local global i32 42
-define i32* @get_strong_local_global() {
+define dso_local i32* @get_strong_local_global() {
ret i32* @strong_local_global
}
; CHECK: leaq .Lstrong_local_global$local(%rip), %rax
@@ -53,7 +53,7 @@ define i32* @get_strong_local_global() {
; CHECK32: leal .Lstrong_local_global$local at GOTOFF(%eax), %eax
@weak_local_global = weak dso_local global i32 42
-define i32* @get_weak_local_global() {
+define dso_local i32* @get_weak_local_global() {
ret i32* @weak_local_global
}
; CHECK: leaq weak_local_global(%rip), %rax
@@ -61,7 +61,7 @@ define i32* @get_weak_local_global() {
; CHECK32: leal weak_local_global at GOTOFF(%eax), %eax
@external_local_global = external dso_local global i32
-define i32* @get_external_local_global() {
+define dso_local i32* @get_external_local_global() {
ret i32* @external_local_global
}
; CHECK: leaq external_local_global(%rip), %rax
@@ -70,7 +70,7 @@ define i32* @get_external_local_global() {
@strong_preemptable_global = dso_preemptable global i32 42
-define i32* @get_strong_preemptable_global() {
+define dso_local i32* @get_strong_preemptable_global() {
ret i32* @strong_preemptable_global
}
; CHECK: movq strong_preemptable_global at GOTPCREL(%rip), %rax
@@ -78,7 +78,7 @@ define i32* @get_strong_preemptable_global() {
; CHECK32: movl strong_preemptable_global at GOT(%eax), %eax
@weak_preemptable_global = weak dso_preemptable global i32 42
-define i32* @get_weak_preemptable_global() {
+define dso_local i32* @get_weak_preemptable_global() {
ret i32* @weak_preemptable_global
}
; CHECK: movq weak_preemptable_global at GOTPCREL(%rip), %rax
@@ -86,7 +86,7 @@ define i32* @get_weak_preemptable_global() {
; CHECK32: movl weak_preemptable_global at GOT(%eax), %eax
@external_preemptable_global = external dso_preemptable global i32
-define i32* @get_external_preemptable_global() {
+define dso_local i32* @get_external_preemptable_global() {
ret i32* @external_preemptable_global
}
; CHECK: movq external_preemptable_global at GOTPCREL(%rip), %rax
@@ -94,10 +94,10 @@ define i32* @get_external_preemptable_global() {
; CHECK32: movl external_preemptable_global at GOT(%eax), %eax
; aliases
- at aliasee = global i32 42
+ at aliasee = dso_local global i32 42
@strong_default_alias = alias i32, i32* @aliasee
-define i32* @get_strong_default_alias() {
+define dso_local i32* @get_strong_default_alias() {
ret i32* @strong_default_alias
}
; CHECK: movq strong_default_alias at GOTPCREL(%rip), %rax
@@ -105,7 +105,7 @@ define i32* @get_strong_default_alias() {
; CHECK32: movl strong_default_alias at GOT(%eax), %eax
@strong_hidden_alias = hidden alias i32, i32* @aliasee
-define i32* @get_strong_hidden_alias() {
+define dso_local i32* @get_strong_hidden_alias() {
ret i32* @strong_hidden_alias
}
; CHECK: leaq strong_hidden_alias(%rip), %rax
@@ -113,7 +113,7 @@ define i32* @get_strong_hidden_alias() {
; CHECK32: leal strong_hidden_alias at GOTOFF(%eax), %eax
@weak_default_alias = weak alias i32, i32* @aliasee
-define i32* @get_weak_default_alias() {
+define dso_local i32* @get_weak_default_alias() {
ret i32* @weak_default_alias
}
; CHECK: movq weak_default_alias at GOTPCREL(%rip), %rax
@@ -121,7 +121,7 @@ define i32* @get_weak_default_alias() {
; CHECK32: movl weak_default_alias at GOT(%eax), %eax
@strong_local_alias = dso_local alias i32, i32* @aliasee
-define i32* @get_strong_local_alias() {
+define dso_local i32* @get_strong_local_alias() {
ret i32* @strong_local_alias
}
; CHECK: leaq .Lstrong_local_alias$local(%rip), %rax
@@ -129,7 +129,7 @@ define i32* @get_strong_local_alias() {
; CHECK32: leal .Lstrong_local_alias$local at GOTOFF(%eax), %eax
@weak_local_alias = weak dso_local alias i32, i32* @aliasee
-define i32* @get_weak_local_alias() {
+define dso_local i32* @get_weak_local_alias() {
ret i32* @weak_local_alias
}
; CHECK: leaq weak_local_alias(%rip), %rax
@@ -138,7 +138,7 @@ define i32* @get_weak_local_alias() {
@strong_preemptable_alias = dso_preemptable alias i32, i32* @aliasee
-define i32* @get_strong_preemptable_alias() {
+define dso_local i32* @get_strong_preemptable_alias() {
ret i32* @strong_preemptable_alias
}
; CHECK: movq strong_preemptable_alias at GOTPCREL(%rip), %rax
@@ -146,7 +146,7 @@ define i32* @get_strong_preemptable_alias() {
; CHECK32: movl strong_preemptable_alias at GOT(%eax), %eax
@weak_preemptable_alias = weak dso_preemptable alias i32, i32* @aliasee
-define i32* @get_weak_preemptable_alias() {
+define dso_local i32* @get_weak_preemptable_alias() {
ret i32* @weak_preemptable_alias
}
; CHECK: movq weak_preemptable_alias at GOTPCREL(%rip), %rax
@@ -155,10 +155,10 @@ define i32* @get_weak_preemptable_alias() {
; functions
-define void @strong_default_function() {
+define dso_local void @strong_default_function() {
ret void
}
-define void()* @get_strong_default_function() {
+define dso_local void()* @get_strong_default_function() {
ret void()* @strong_default_function
}
; CHECK: movq strong_default_function at GOTPCREL(%rip), %rax
@@ -168,17 +168,17 @@ define void()* @get_strong_default_function() {
define hidden void @strong_hidden_function() {
ret void
}
-define void()* @get_strong_hidden_function() {
+define dso_local void()* @get_strong_hidden_function() {
ret void()* @strong_hidden_function
}
; CHECK: leaq strong_hidden_function(%rip), %rax
; STATIC: movl $strong_hidden_function, %eax
; CHECK32: leal strong_hidden_function at GOTOFF(%eax), %eax
-define weak void @weak_default_function() {
+define weak dso_local void @weak_default_function() {
ret void
}
-define void()* @get_weak_default_function() {
+define dso_local void()* @get_weak_default_function() {
ret void()* @weak_default_function
}
; CHECK: movq weak_default_function at GOTPCREL(%rip), %rax
@@ -186,7 +186,7 @@ define void()* @get_weak_default_function() {
; CHECK32: movl weak_default_function at GOT(%eax), %eax
declare void @external_default_function()
-define void()* @get_external_default_function() {
+define dso_local void()* @get_external_default_function() {
ret void()* @external_default_function
}
; CHECK: movq external_default_function at GOTPCREL(%rip), %rax
@@ -196,7 +196,7 @@ define void()* @get_external_default_function() {
define dso_local void @strong_local_function() {
ret void
}
-define void()* @get_strong_local_function() {
+define dso_local void()* @get_strong_local_function() {
ret void()* @strong_local_function
}
; COMMON: {{^}}strong_local_function:
@@ -208,7 +208,7 @@ define void()* @get_strong_local_function() {
define weak dso_local void @weak_local_function() {
ret void
}
-define void()* @get_weak_local_function() {
+define dso_local void()* @get_weak_local_function() {
ret void()* @weak_local_function
}
; CHECK: leaq weak_local_function(%rip), %rax
@@ -216,7 +216,7 @@ define void()* @get_weak_local_function() {
; CHECK32: leal weak_local_function at GOTOFF(%eax), %eax
declare dso_local void @external_local_function()
-define void()* @get_external_local_function() {
+define dso_local void()* @get_external_local_function() {
ret void()* @external_local_function
}
; CHECK: leaq external_local_function(%rip), %rax
@@ -227,7 +227,7 @@ define void()* @get_external_local_function() {
define dso_preemptable void @strong_preemptable_function() {
ret void
}
-define void()* @get_strong_preemptable_function() {
+define dso_local void()* @get_strong_preemptable_function() {
ret void()* @strong_preemptable_function
}
; CHECK: movq strong_preemptable_function at GOTPCREL(%rip), %rax
@@ -237,7 +237,7 @@ define void()* @get_strong_preemptable_function() {
define weak dso_preemptable void @weak_preemptable_function() {
ret void
}
-define void()* @get_weak_preemptable_function() {
+define dso_local void()* @get_weak_preemptable_function() {
ret void()* @weak_preemptable_function
}
; CHECK: movq weak_preemptable_function at GOTPCREL(%rip), %rax
@@ -245,7 +245,7 @@ define void()* @get_weak_preemptable_function() {
; CHECK32: movl weak_preemptable_function at GOT(%eax), %eax
declare dso_preemptable void @external_preemptable_function()
-define void()* @get_external_preemptable_function() {
+define dso_local void()* @get_external_preemptable_function() {
ret void()* @external_preemptable_function
}
; CHECK: movq external_preemptable_function at GOTPCREL(%rip), %rax
diff --git a/llvm/test/CodeGen/X86/load-partial.ll b/llvm/test/CodeGen/X86/load-partial.ll
index 4f60c4475f19..9e999bb073ee 100644
--- a/llvm/test/CodeGen/X86/load-partial.ll
+++ b/llvm/test/CodeGen/X86/load-partial.ll
@@ -301,8 +301,8 @@ define <4 x double> @load_double4_0u2u(double* nocapture readonly dereferenceabl
}
; Test case identified in rL366501
- at h = local_unnamed_addr global i8 0, align 1
-define i32 @load_partial_illegal_type() {
+ at h = dso_local local_unnamed_addr global i8 0, align 1
+define dso_local i32 @load_partial_illegal_type() {
; SSE2-LABEL: load_partial_illegal_type:
; SSE2: # %bb.0:
; SSE2-NEXT: movzwl {{.*}}(%rip), %eax
@@ -345,7 +345,7 @@ define i32 @load_partial_illegal_type() {
ret i32 %4
}
-define void @PR43227(i32* %explicit_0, <8 x i32>* %explicit_1) {
+define dso_local void @PR43227(i32* %explicit_0, <8 x i32>* %explicit_1) {
; SSE-LABEL: PR43227:
; SSE: # %bb.0:
; SSE-NEXT: movq {{.*#+}} xmm0 = mem[0],zero
diff --git a/llvm/test/CodeGen/X86/lsr-sort.ll b/llvm/test/CodeGen/X86/lsr-sort.ll
index e831e9b20f2e..1a809525706e 100644
--- a/llvm/test/CodeGen/X86/lsr-sort.ll
+++ b/llvm/test/CodeGen/X86/lsr-sort.ll
@@ -1,9 +1,9 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=x86_64-- | FileCheck %s
- at X = common global i16 0 ; <i16*> [#uses=1]
+ at X = common dso_local global i16 0 ; <i16*> [#uses=1]
-define i32 @foo(i32 %N) nounwind {
+define dso_local i32 @foo(i32 %N) nounwind {
; CHECK-LABEL: foo:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xorl %eax, %eax
diff --git a/llvm/test/CodeGen/X86/mempcpy.ll b/llvm/test/CodeGen/X86/mempcpy.ll
index f8db255c1a4b..c2837fde60ed 100644
--- a/llvm/test/CodeGen/X86/mempcpy.ll
+++ b/llvm/test/CodeGen/X86/mempcpy.ll
@@ -13,14 +13,14 @@
; Also see mempcpy-32.ll
- at G = common global i8* null, align 8
+ at G = common dso_local global i8* null, align 8
; CHECK-LABEL: RET_MEMPCPY:
; CHECK: movq [[REG:%r[a-z0-9]+]], {{.*}}G
; CHECK: callq {{.*}}memcpy
; CHECK: movq [[REG]], %rax
;
-define i8* @RET_MEMPCPY(i8* %DST, i8* %SRC, i64 %N) {
+define dso_local i8* @RET_MEMPCPY(i8* %DST, i8* %SRC, i64 %N) {
%add.ptr = getelementptr inbounds i8, i8* %DST, i64 %N
store i8* %add.ptr, i8** @G, align 8
%call = tail call i8* @mempcpy(i8* %DST, i8* %SRC, i64 %N)
diff --git a/llvm/test/CodeGen/X86/min-legal-vector-width.ll b/llvm/test/CodeGen/X86/min-legal-vector-width.ll
index 5456cd2e753a..d7485c08e3df 100644
--- a/llvm/test/CodeGen/X86/min-legal-vector-width.ll
+++ b/llvm/test/CodeGen/X86/min-legal-vector-width.ll
@@ -12,7 +12,7 @@
; This file primarily contains tests for specific places in X86ISelLowering.cpp that needed be made aware of the legalizer not allowing 512-bit vectors due to prefer-256-bit even though AVX512 is enabled.
-define void @add256(<16 x i32>* %a, <16 x i32>* %b, <16 x i32>* %c) "min-legal-vector-width"="256" {
+define dso_local void @add256(<16 x i32>* %a, <16 x i32>* %b, <16 x i32>* %c) "min-legal-vector-width"="256" {
; CHECK-LABEL: add256:
; CHECK: # %bb.0:
; CHECK-NEXT: vmovdqa (%rdi), %ymm0
@@ -30,7 +30,7 @@ define void @add256(<16 x i32>* %a, <16 x i32>* %b, <16 x i32>* %c) "min-legal-v
ret void
}
-define void @add512(<16 x i32>* %a, <16 x i32>* %b, <16 x i32>* %c) "min-legal-vector-width"="512" {
+define dso_local void @add512(<16 x i32>* %a, <16 x i32>* %b, <16 x i32>* %c) "min-legal-vector-width"="512" {
; CHECK-LABEL: add512:
; CHECK: # %bb.0:
; CHECK-NEXT: vmovdqa64 (%rdi), %zmm0
@@ -45,7 +45,7 @@ define void @add512(<16 x i32>* %a, <16 x i32>* %b, <16 x i32>* %c) "min-legal-v
ret void
}
-define void @avg_v64i8_256(<64 x i8>* %a, <64 x i8>* %b) "min-legal-vector-width"="256" {
+define dso_local void @avg_v64i8_256(<64 x i8>* %a, <64 x i8>* %b) "min-legal-vector-width"="256" {
; CHECK-LABEL: avg_v64i8_256:
; CHECK: # %bb.0:
; CHECK-NEXT: vmovdqa (%rsi), %ymm0
@@ -69,7 +69,7 @@ define void @avg_v64i8_256(<64 x i8>* %a, <64 x i8>* %b) "min-legal-vector-width
}
-define void @avg_v64i8_512(<64 x i8>* %a, <64 x i8>* %b) "min-legal-vector-width"="512" {
+define dso_local void @avg_v64i8_512(<64 x i8>* %a, <64 x i8>* %b) "min-legal-vector-width"="512" {
; CHECK-LABEL: avg_v64i8_512:
; CHECK: # %bb.0:
; CHECK-NEXT: vmovdqa64 (%rsi), %zmm0
@@ -89,7 +89,7 @@ define void @avg_v64i8_512(<64 x i8>* %a, <64 x i8>* %b) "min-legal-vector-width
ret void
}
-define void @pmaddwd_32_256(<32 x i16>* %APtr, <32 x i16>* %BPtr, <16 x i32>* %CPtr) "min-legal-vector-width"="256" {
+define dso_local void @pmaddwd_32_256(<32 x i16>* %APtr, <32 x i16>* %BPtr, <16 x i32>* %CPtr) "min-legal-vector-width"="256" {
; CHECK-LABEL: pmaddwd_32_256:
; CHECK: # %bb.0:
; CHECK-NEXT: vmovdqa (%rdi), %ymm0
@@ -112,7 +112,7 @@ define void @pmaddwd_32_256(<32 x i16>* %APtr, <32 x i16>* %BPtr, <16 x i32>* %C
ret void
}
-define void @pmaddwd_32_512(<32 x i16>* %APtr, <32 x i16>* %BPtr, <16 x i32>* %CPtr) "min-legal-vector-width"="512" {
+define dso_local void @pmaddwd_32_512(<32 x i16>* %APtr, <32 x i16>* %BPtr, <16 x i32>* %CPtr) "min-legal-vector-width"="512" {
; CHECK-LABEL: pmaddwd_32_512:
; CHECK: # %bb.0:
; CHECK-NEXT: vmovdqa64 (%rdi), %zmm0
@@ -132,7 +132,7 @@ define void @pmaddwd_32_512(<32 x i16>* %APtr, <32 x i16>* %BPtr, <16 x i32>* %C
ret void
}
-define void @psubus_64i8_max_256(<64 x i8>* %xptr, <64 x i8>* %yptr, <64 x i8>* %zptr) "min-legal-vector-width"="256" {
+define dso_local void @psubus_64i8_max_256(<64 x i8>* %xptr, <64 x i8>* %yptr, <64 x i8>* %zptr) "min-legal-vector-width"="256" {
; CHECK-LABEL: psubus_64i8_max_256:
; CHECK: # %bb.0:
; CHECK-NEXT: vmovdqa (%rdi), %ymm0
@@ -152,7 +152,7 @@ define void @psubus_64i8_max_256(<64 x i8>* %xptr, <64 x i8>* %yptr, <64 x i8>*
ret void
}
-define void @psubus_64i8_max_512(<64 x i8>* %xptr, <64 x i8>* %yptr, <64 x i8>* %zptr) "min-legal-vector-width"="512" {
+define dso_local void @psubus_64i8_max_512(<64 x i8>* %xptr, <64 x i8>* %yptr, <64 x i8>* %zptr) "min-legal-vector-width"="512" {
; CHECK-LABEL: psubus_64i8_max_512:
; CHECK: # %bb.0:
; CHECK-NEXT: vmovdqa64 (%rdi), %zmm0
@@ -169,7 +169,7 @@ define void @psubus_64i8_max_512(<64 x i8>* %xptr, <64 x i8>* %yptr, <64 x i8>*
ret void
}
-define i32 @_Z9test_charPcS_i_256(i8* nocapture readonly, i8* nocapture readonly, i32) "min-legal-vector-width"="256" {
+define dso_local i32 @_Z9test_charPcS_i_256(i8* nocapture readonly, i8* nocapture readonly, i32) "min-legal-vector-width"="256" {
; CHECK-LABEL: _Z9test_charPcS_i_256:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: movl %edx, %eax
@@ -240,7 +240,7 @@ middle.block:
ret i32 %13
}
-define i32 @_Z9test_charPcS_i_512(i8* nocapture readonly, i8* nocapture readonly, i32) "min-legal-vector-width"="512" {
+define dso_local i32 @_Z9test_charPcS_i_512(i8* nocapture readonly, i8* nocapture readonly, i32) "min-legal-vector-width"="512" {
; CHECK-LABEL: _Z9test_charPcS_i_512:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: movl %edx, %eax
@@ -306,10 +306,10 @@ middle.block:
ret i32 %13
}
- at a = global [1024 x i8] zeroinitializer, align 16
- at b = global [1024 x i8] zeroinitializer, align 16
+ at a = dso_local global [1024 x i8] zeroinitializer, align 16
+ at b = dso_local global [1024 x i8] zeroinitializer, align 16
-define i32 @sad_16i8_256() "min-legal-vector-width"="256" {
+define dso_local i32 @sad_16i8_256() "min-legal-vector-width"="256" {
; CHECK-LABEL: sad_16i8_256:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vpxor %xmm0, %xmm0, %xmm0
@@ -370,7 +370,7 @@ middle.block:
ret i32 %12
}
-define i32 @sad_16i8_512() "min-legal-vector-width"="512" {
+define dso_local i32 @sad_16i8_512() "min-legal-vector-width"="512" {
; CHECK-LABEL: sad_16i8_512:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vpxor %xmm0, %xmm0, %xmm0
@@ -431,7 +431,7 @@ middle.block:
ret i32 %12
}
-define void @sbto16f32_256(<16 x i16> %a, <16 x float>* %res) "min-legal-vector-width"="256" {
+define dso_local void @sbto16f32_256(<16 x i16> %a, <16 x float>* %res) "min-legal-vector-width"="256" {
; CHECK-LABEL: sbto16f32_256:
; CHECK: # %bb.0:
; CHECK-NEXT: vpmovw2m %ymm0, %k0
@@ -450,7 +450,7 @@ define void @sbto16f32_256(<16 x i16> %a, <16 x float>* %res) "min-legal-vector-
ret void
}
-define void @sbto16f32_512(<16 x i16> %a, <16 x float>* %res) "min-legal-vector-width"="512" {
+define dso_local void @sbto16f32_512(<16 x i16> %a, <16 x float>* %res) "min-legal-vector-width"="512" {
; CHECK-LABEL: sbto16f32_512:
; CHECK: # %bb.0:
; CHECK-NEXT: vpmovw2m %ymm0, %k0
@@ -465,7 +465,7 @@ define void @sbto16f32_512(<16 x i16> %a, <16 x float>* %res) "min-legal-vector-
ret void
}
-define void @sbto16f64_256(<16 x i16> %a, <16 x double>* %res) "min-legal-vector-width"="256" {
+define dso_local void @sbto16f64_256(<16 x i16> %a, <16 x double>* %res) "min-legal-vector-width"="256" {
; CHECK-LABEL: sbto16f64_256:
; CHECK: # %bb.0:
; CHECK-NEXT: vpmovw2m %ymm0, %k0
@@ -490,7 +490,7 @@ define void @sbto16f64_256(<16 x i16> %a, <16 x double>* %res) "min-legal-vecto
ret void
}
-define void @sbto16f64_512(<16 x i16> %a, <16 x double>* %res) "min-legal-vector-width"="512" {
+define dso_local void @sbto16f64_512(<16 x i16> %a, <16 x double>* %res) "min-legal-vector-width"="512" {
; CHECK-LABEL: sbto16f64_512:
; CHECK: # %bb.0:
; CHECK-NEXT: vpmovw2m %ymm0, %k0
@@ -508,7 +508,7 @@ define void @sbto16f64_512(<16 x i16> %a, <16 x double>* %res) "min-legal-vecto
ret void
}
-define void @ubto16f32_256(<16 x i16> %a, <16 x float>* %res) "min-legal-vector-width"="256" {
+define dso_local void @ubto16f32_256(<16 x i16> %a, <16 x float>* %res) "min-legal-vector-width"="256" {
; CHECK-LABEL: ubto16f32_256:
; CHECK: # %bb.0:
; CHECK-NEXT: vpmovw2m %ymm0, %k0
@@ -529,7 +529,7 @@ define void @ubto16f32_256(<16 x i16> %a, <16 x float>* %res) "min-legal-vector-
ret void
}
-define void @ubto16f32_512(<16 x i16> %a, <16 x float>* %res) "min-legal-vector-width"="512" {
+define dso_local void @ubto16f32_512(<16 x i16> %a, <16 x float>* %res) "min-legal-vector-width"="512" {
; CHECK-LABEL: ubto16f32_512:
; CHECK: # %bb.0:
; CHECK-NEXT: vpmovw2m %ymm0, %k0
@@ -545,7 +545,7 @@ define void @ubto16f32_512(<16 x i16> %a, <16 x float>* %res) "min-legal-vector-
ret void
}
-define void @ubto16f64_256(<16 x i16> %a, <16 x double>* %res) "min-legal-vector-width"="256" {
+define dso_local void @ubto16f64_256(<16 x i16> %a, <16 x double>* %res) "min-legal-vector-width"="256" {
; CHECK-LABEL: ubto16f64_256:
; CHECK: # %bb.0:
; CHECK-NEXT: vpmovw2m %ymm0, %k0
@@ -572,7 +572,7 @@ define void @ubto16f64_256(<16 x i16> %a, <16 x double>* %res) "min-legal-vector
ret void
}
-define void @ubto16f64_512(<16 x i16> %a, <16 x double>* %res) "min-legal-vector-width"="512" {
+define dso_local void @ubto16f64_512(<16 x i16> %a, <16 x double>* %res) "min-legal-vector-width"="512" {
; CHECK-LABEL: ubto16f64_512:
; CHECK: # %bb.0:
; CHECK-NEXT: vpmovw2m %ymm0, %k0
@@ -652,7 +652,7 @@ define <16 x i16> @test_16f32tosb_512(<16 x float>* %ptr, <16 x i16> %passthru)
ret <16 x i16> %select
}
-define void @mul256(<64 x i8>* %a, <64 x i8>* %b, <64 x i8>* %c) "min-legal-vector-width"="256" {
+define dso_local void @mul256(<64 x i8>* %a, <64 x i8>* %b, <64 x i8>* %c) "min-legal-vector-width"="256" {
; CHECK-AVX512-LABEL: mul256:
; CHECK-AVX512: # %bb.0:
; CHECK-AVX512-NEXT: vmovdqa (%rdi), %ymm0
@@ -715,7 +715,7 @@ define void @mul256(<64 x i8>* %a, <64 x i8>* %b, <64 x i8>* %c) "min-legal-vect
ret void
}
-define void @mul512(<64 x i8>* %a, <64 x i8>* %b, <64 x i8>* %c) "min-legal-vector-width"="512" {
+define dso_local void @mul512(<64 x i8>* %a, <64 x i8>* %b, <64 x i8>* %c) "min-legal-vector-width"="512" {
; CHECK-AVX512-LABEL: mul512:
; CHECK-AVX512: # %bb.0:
; CHECK-AVX512-NEXT: vmovdqa64 (%rdi), %zmm0
@@ -945,7 +945,7 @@ define <32 x i8> @trunc_v32i16_v32i8_sign(<32 x i16>* %x) nounwind "min-legal-ve
ret <32 x i8> %c
}
-define void @zext_v16i8_v16i64(<16 x i8> %x, <16 x i64>* %y) nounwind "min-legal-vector-width"="256" {
+define dso_local void @zext_v16i8_v16i64(<16 x i8> %x, <16 x i64>* %y) nounwind "min-legal-vector-width"="256" {
; CHECK-LABEL: zext_v16i8_v16i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vpmovzxbw {{.*#+}} ymm1 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero,xmm0[8],zero,xmm0[9],zero,xmm0[10],zero,xmm0[11],zero,xmm0[12],zero,xmm0[13],zero,xmm0[14],zero,xmm0[15],zero
@@ -967,7 +967,7 @@ define void @zext_v16i8_v16i64(<16 x i8> %x, <16 x i64>* %y) nounwind "min-legal
ret void
}
-define void @sext_v16i8_v16i64(<16 x i8> %x, <16 x i64>* %y) nounwind "min-legal-vector-width"="256" {
+define dso_local void @sext_v16i8_v16i64(<16 x i8> %x, <16 x i64>* %y) nounwind "min-legal-vector-width"="256" {
; CHECK-LABEL: sext_v16i8_v16i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vpmovsxbw %xmm0, %ymm1
@@ -989,7 +989,7 @@ define void @sext_v16i8_v16i64(<16 x i8> %x, <16 x i64>* %y) nounwind "min-legal
ret void
}
-define void @vselect_split_v8i16_setcc(<8 x i16> %s, <8 x i16> %t, <8 x i64>* %p, <8 x i64>* %q, <8 x i64>* %r) "min-legal-vector-width"="256" {
+define dso_local void @vselect_split_v8i16_setcc(<8 x i16> %s, <8 x i16> %t, <8 x i64>* %p, <8 x i64>* %q, <8 x i64>* %r) "min-legal-vector-width"="256" {
; CHECK-LABEL: vselect_split_v8i16_setcc:
; CHECK: # %bb.0:
; CHECK-NEXT: vmovdqa (%rsi), %ymm2
@@ -1010,7 +1010,7 @@ define void @vselect_split_v8i16_setcc(<8 x i16> %s, <8 x i16> %t, <8 x i64>* %p
ret void
}
-define void @vselect_split_v8i32_setcc(<8 x i32> %s, <8 x i32> %t, <8 x i64>* %p, <8 x i64>* %q, <8 x i64>* %r) "min-legal-vector-width"="256" {
+define dso_local void @vselect_split_v8i32_setcc(<8 x i32> %s, <8 x i32> %t, <8 x i64>* %p, <8 x i64>* %q, <8 x i64>* %r) "min-legal-vector-width"="256" {
; CHECK-LABEL: vselect_split_v8i32_setcc:
; CHECK: # %bb.0:
; CHECK-NEXT: vmovdqa (%rsi), %ymm2
@@ -1031,7 +1031,7 @@ define void @vselect_split_v8i32_setcc(<8 x i32> %s, <8 x i32> %t, <8 x i64>* %p
ret void
}
-define void @vselect_split_v16i8_setcc(<16 x i8> %s, <16 x i8> %t, <16 x i32>* %p, <16 x i32>* %q, <16 x i32>* %r) "min-legal-vector-width"="256" {
+define dso_local void @vselect_split_v16i8_setcc(<16 x i8> %s, <16 x i8> %t, <16 x i32>* %p, <16 x i32>* %q, <16 x i32>* %r) "min-legal-vector-width"="256" {
; CHECK-LABEL: vselect_split_v16i8_setcc:
; CHECK: # %bb.0:
; CHECK-NEXT: vmovdqa (%rsi), %ymm2
@@ -1052,7 +1052,7 @@ define void @vselect_split_v16i8_setcc(<16 x i8> %s, <16 x i8> %t, <16 x i32>* %
ret void
}
-define void @vselect_split_v16i16_setcc(<16 x i16> %s, <16 x i16> %t, <16 x i32>* %p, <16 x i32>* %q, <16 x i32>* %r) "min-legal-vector-width"="256" {
+define dso_local void @vselect_split_v16i16_setcc(<16 x i16> %s, <16 x i16> %t, <16 x i32>* %p, <16 x i32>* %q, <16 x i32>* %r) "min-legal-vector-width"="256" {
; CHECK-LABEL: vselect_split_v16i16_setcc:
; CHECK: # %bb.0:
; CHECK-NEXT: vmovdqa (%rsi), %ymm2
@@ -1091,7 +1091,7 @@ define <16 x i8> @trunc_packus_v16i32_v16i8(<16 x i32>* %p) "min-legal-vector-wi
ret <16 x i8> %f
}
-define void @trunc_packus_v16i32_v16i8_store(<16 x i32>* %p, <16 x i8>* %q) "min-legal-vector-width"="256" {
+define dso_local void @trunc_packus_v16i32_v16i8_store(<16 x i32>* %p, <16 x i8>* %q) "min-legal-vector-width"="256" {
; CHECK-LABEL: trunc_packus_v16i32_v16i8_store:
; CHECK: # %bb.0:
; CHECK-NEXT: vmovdqa (%rdi), %ymm0
@@ -1117,7 +1117,7 @@ define <64 x i1> @v64i1_argument_return(<64 x i1> %x) "min-legal-vector-width"="
ret <64 x i1> %x
}
-define void @v64i1_shuffle(<64 x i8>* %x, <64 x i8>* %y) "min-legal-vector-width"="256" {
+define dso_local void @v64i1_shuffle(<64 x i8>* %x, <64 x i8>* %y) "min-legal-vector-width"="256" {
; CHECK-LABEL: v64i1_shuffle:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmovdqa (%rdi), %ymm1
@@ -1575,9 +1575,9 @@ entry:
}
declare void @llvm.masked.store.v64i8.p0v64i8(<64 x i8>, <64 x i8>*, i32, <64 x i1>)
- at mem64_dst = global i64 0, align 8
- at mem64_src = global i64 0, align 8
-define i32 @v64i1_inline_asm() "min-legal-vector-width"="256" {
+ at mem64_dst = dso_local global i64 0, align 8
+ at mem64_src = dso_local global i64 0, align 8
+define dso_local i32 @v64i1_inline_asm() "min-legal-vector-width"="256" {
; CHECK-LABEL: v64i1_inline_asm:
; CHECK: # %bb.0:
; CHECK-NEXT: kmovq {{.*}}(%rip), %k0
@@ -1594,7 +1594,7 @@ define i32 @v64i1_inline_asm() "min-legal-vector-width"="256" {
ret i32 %4
}
-define void @cmp_v8i64_sext(<8 x i64>* %xptr, <8 x i64>* %yptr, <8 x i64>* %zptr) "min-legal-vector-width"="256" {
+define dso_local void @cmp_v8i64_sext(<8 x i64>* %xptr, <8 x i64>* %yptr, <8 x i64>* %zptr) "min-legal-vector-width"="256" {
; CHECK-LABEL: cmp_v8i64_sext:
; CHECK: # %bb.0:
; CHECK-NEXT: vmovdqa (%rsi), %ymm0
@@ -1613,7 +1613,7 @@ define void @cmp_v8i64_sext(<8 x i64>* %xptr, <8 x i64>* %yptr, <8 x i64>* %zptr
ret void
}
-define void @cmp_v8i64_zext(<8 x i64>* %xptr, <8 x i64>* %yptr, <8 x i64>* %zptr) "min-legal-vector-width"="256" {
+define dso_local void @cmp_v8i64_zext(<8 x i64>* %xptr, <8 x i64>* %yptr, <8 x i64>* %zptr) "min-legal-vector-width"="256" {
; CHECK-LABEL: cmp_v8i64_zext:
; CHECK: # %bb.0:
; CHECK-NEXT: vmovdqa (%rsi), %ymm0
diff --git a/llvm/test/CodeGen/X86/ms-inline-asm-PR44272.ll b/llvm/test/CodeGen/X86/ms-inline-asm-PR44272.ll
index ea66ca3ea3b3..3d8a4fe385c5 100644
--- a/llvm/test/CodeGen/X86/ms-inline-asm-PR44272.ll
+++ b/llvm/test/CodeGen/X86/ms-inline-asm-PR44272.ll
@@ -1,12 +1,12 @@
; RUN: llc < %s -mtriple=i686-- | FileCheck %s
; RUN: llc < %s -mtriple=x86_64-- | FileCheck %s
-define void @func() {
+define dso_local void @func() {
entry:
ret void
}
-define void @main() {
+define dso_local void @main() {
entry:
call void asm sideeffect inteldialect "call ${0:P}", "*m,~{dirflag},~{fpsr},~{flags}"(void ()* @func)
ret void
diff --git a/llvm/test/CodeGen/X86/musttail-tailcc.ll b/llvm/test/CodeGen/X86/musttail-tailcc.ll
index 9413e6aa45f5..54dcab2c5fe7 100644
--- a/llvm/test/CodeGen/X86/musttail-tailcc.ll
+++ b/llvm/test/CodeGen/X86/musttail-tailcc.ll
@@ -6,7 +6,7 @@
declare dso_local tailcc i32 @tailcallee(i32 %a1, i32 %a2)
-define tailcc i32 @tailcaller(i32 %in1, i32 %in2) nounwind {
+define dso_local tailcc i32 @tailcaller(i32 %in1, i32 %in2) nounwind {
; X64-LABEL: tailcaller:
; X64: # %bb.0: # %entry
; X64-NEXT: jmp tailcallee # TAILCALL
@@ -35,7 +35,7 @@ define tailcc noalias i8* @noalias_caller() nounwind {
declare dso_local tailcc noalias i8* @noalias_callee()
-define tailcc i8* @alias_caller() nounwind {
+define dso_local tailcc i8* @alias_caller() nounwind {
; X64-LABEL: alias_caller:
; X64: # %bb.0:
; X64-NEXT: jmp noalias_callee # TAILCALL
@@ -47,7 +47,7 @@ define tailcc i8* @alias_caller() nounwind {
ret i8* %p
}
-define tailcc void @void_test(i32, i32, i32, i32) {
+define dso_local tailcc void @void_test(i32, i32, i32, i32) {
; X64-LABEL: void_test:
; X64: # %bb.0: # %entry
; X64-NEXT: jmp void_test # TAILCALL
@@ -69,7 +69,7 @@ define tailcc void @void_test(i32, i32, i32, i32) {
ret void
}
-define tailcc i1 @i1test(i32, i32, i32, i32) {
+define dso_local tailcc i1 @i1test(i32, i32, i32, i32) {
; X64-LABEL: i1test:
; X64: # %bb.0: # %entry
; X64-NEXT: jmp i1test # TAILCALL
diff --git a/llvm/test/CodeGen/X86/narrow_op-1.ll b/llvm/test/CodeGen/X86/narrow_op-1.ll
index dc24b190ea91..8e6eda095156 100644
--- a/llvm/test/CodeGen/X86/narrow_op-1.ll
+++ b/llvm/test/CodeGen/X86/narrow_op-1.ll
@@ -2,9 +2,9 @@
; RUN: llc < %s -mtriple=x86_64-- | FileCheck %s
%struct.bf = type { i64, i16, i16, i32 }
- at bfi = common global %struct.bf zeroinitializer, align 16
+ at bfi = common dso_local global %struct.bf zeroinitializer, align 16
-define void @t1() nounwind optsize ssp {
+define dso_local void @t1() nounwind optsize ssp {
; CHECK-LABEL: t1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: orb $1, bfi+{{.*}}(%rip)
@@ -17,7 +17,7 @@ entry:
}
-define void @t2() nounwind optsize ssp {
+define dso_local void @t2() nounwind optsize ssp {
; CHECK-LABEL: t2:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: orl $16842752, bfi+{{.*}}(%rip) # imm = 0x1010000
diff --git a/llvm/test/CodeGen/X86/peephole-fold-movsd.ll b/llvm/test/CodeGen/X86/peephole-fold-movsd.ll
index fbfa0d474846..bdff8541a50e 100644
--- a/llvm/test/CodeGen/X86/peephole-fold-movsd.ll
+++ b/llvm/test/CodeGen/X86/peephole-fold-movsd.ll
@@ -7,11 +7,11 @@
%struct.S1 = type { double, double }
- at g = common global %struct.S1 zeroinitializer, align 8
+ at g = common dso_local global %struct.S1 zeroinitializer, align 8
declare void @foo3(%struct.S1*)
-define void @foo1(double %a.coerce0, double %a.coerce1, double %b.coerce0, double %b.coerce1) nounwind {
+define dso_local void @foo1(double %a.coerce0, double %a.coerce1, double %b.coerce0, double %b.coerce1) nounwind {
; CHECK-LABEL: foo1:
; CHECK: # %bb.0:
; CHECK-NEXT: subq $24, %rsp
diff --git a/llvm/test/CodeGen/X86/pie.ll b/llvm/test/CodeGen/X86/pie.ll
index 7b765f8ef54a..f557765cf910 100644
--- a/llvm/test/CodeGen/X86/pie.ll
+++ b/llvm/test/CodeGen/X86/pie.ll
@@ -10,11 +10,11 @@
; CHECK: call{{l|q}} internal_foo{{$}}
; CHECK: call{{l|q}} ext_baz at PLT
-define weak void @weak_foo() {
+define weak dso_local void @weak_foo() {
ret void
}
-define weak_odr void @weak_odr_foo() {
+define weak_odr dso_local void @weak_odr_foo() {
ret void
}
@@ -24,11 +24,11 @@ define internal void @internal_foo() {
declare i32 @ext_baz()
-define void @foo() {
+define dso_local void @foo() {
ret void
}
-define void @bar() {
+define dso_local void @bar() {
entry:
call void @foo()
call void @weak_odr_foo()
diff --git a/llvm/test/CodeGen/X86/pr22774.ll b/llvm/test/CodeGen/X86/pr22774.ll
index 00fb4539aff5..8e60f984aa9f 100644
--- a/llvm/test/CodeGen/X86/pr22774.ll
+++ b/llvm/test/CodeGen/X86/pr22774.ll
@@ -1,10 +1,10 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=x86_64-pc-linux-gnu -mattr=+avx < %s | FileCheck %s
- at in = global <4 x i64> <i64 -1, i64 -1, i64 -1, i64 -1>, align 32
- at out = global <2 x i64> zeroinitializer, align 16
+ at in = dso_local global <4 x i64> <i64 -1, i64 -1, i64 -1, i64 -1>, align 32
+ at out = dso_local global <2 x i64> zeroinitializer, align 16
-define i32 @_Z3foov() {
+define dso_local i32 @_Z3foov() {
; CHECK-LABEL: _Z3foov:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
diff --git a/llvm/test/CodeGen/X86/pr31956.ll b/llvm/test/CodeGen/X86/pr31956.ll
index b8c8b9c12919..50e98f689b2d 100644
--- a/llvm/test/CodeGen/X86/pr31956.ll
+++ b/llvm/test/CodeGen/X86/pr31956.ll
@@ -3,8 +3,8 @@
target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
target triple = "x86_64-scei-ps4"
- at G1 = common global <2 x float> zeroinitializer, align 8
- at G2 = common global <8 x float> zeroinitializer, align 32
+ at G1 = common dso_local global <2 x float> zeroinitializer, align 8
+ at G2 = common dso_local global <8 x float> zeroinitializer, align 32
define <4 x float> @foo() {
; CHECK-LABEL: foo:
diff --git a/llvm/test/CodeGen/X86/pr32282.ll b/llvm/test/CodeGen/X86/pr32282.ll
index 8134a7d0a393..f8ef8fcaf8a8 100644
--- a/llvm/test/CodeGen/X86/pr32282.ll
+++ b/llvm/test/CodeGen/X86/pr32282.ll
@@ -4,12 +4,12 @@
; Check for assert in foldMaskAndShiftToScale due to out of range mask scaling.
- at b = common global i8 zeroinitializer, align 1
- at c = common global i8 zeroinitializer, align 1
- at d = common global i64 zeroinitializer, align 8
- at e = common global i64 zeroinitializer, align 8
+ at b = common dso_local global i8 zeroinitializer, align 1
+ at c = common dso_local global i8 zeroinitializer, align 1
+ at d = common dso_local global i64 zeroinitializer, align 8
+ at e = common dso_local global i64 zeroinitializer, align 8
-define void @foo(i64 %x) nounwind {
+define dso_local void @foo(i64 %x) nounwind {
; X86-LABEL: foo:
; X86: # %bb.0:
; X86-NEXT: pushl %eax
diff --git a/llvm/test/CodeGen/X86/pr33290.ll b/llvm/test/CodeGen/X86/pr33290.ll
index 28ac4d43c3ee..457ba48b82c1 100644
--- a/llvm/test/CodeGen/X86/pr33290.ll
+++ b/llvm/test/CodeGen/X86/pr33290.ll
@@ -2,11 +2,11 @@
; RUN: llc < %s -mtriple=i686-unknown-unknown | FileCheck %s --check-prefix=X86
; RUN: llc < %s -mtriple=x86_64-unknown-unknown | FileCheck %s --check-prefix=X64
- at a = common global i32 0, align 4
- at c = common local_unnamed_addr global i8 0, align 1
- at b = common local_unnamed_addr global i32* null, align 8
+ at a = common dso_local global i32 0, align 4
+ at c = common dso_local local_unnamed_addr global i8 0, align 1
+ at b = common dso_local local_unnamed_addr global i32* null, align 8
-define void @e() {
+define dso_local void @e() {
; X86-LABEL: e:
; X86: # %bb.0: # %entry
; X86-NEXT: movl b, %eax
diff --git a/llvm/test/CodeGen/X86/pr34629.ll b/llvm/test/CodeGen/X86/pr34629.ll
index fcd33c80a441..16cf53a3e925 100644
--- a/llvm/test/CodeGen/X86/pr34629.ll
+++ b/llvm/test/CodeGen/X86/pr34629.ll
@@ -4,11 +4,11 @@
target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"
- at b = common local_unnamed_addr global i64 0, align 8
- at a = common local_unnamed_addr global i8 0, align 1
+ at b = common dso_local local_unnamed_addr global i64 0, align 8
+ at a = common dso_local local_unnamed_addr global i8 0, align 1
; Function Attrs: norecurse nounwind uwtable
-define void @c() local_unnamed_addr #0 {
+define dso_local void @c() local_unnamed_addr #0 {
; CHECK-LABEL: c:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: movq {{.*}}(%rip), %rax
diff --git a/llvm/test/CodeGen/X86/pr34634.ll b/llvm/test/CodeGen/X86/pr34634.ll
index 02b34da45b56..3825db7a303b 100644
--- a/llvm/test/CodeGen/X86/pr34634.ll
+++ b/llvm/test/CodeGen/X86/pr34634.ll
@@ -3,12 +3,12 @@
target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"
- at a = common local_unnamed_addr global [1 x [10 x i32]] zeroinitializer, align 16
- at c = common local_unnamed_addr global i32 0, align 4
- at b = common local_unnamed_addr global [1 x [7 x i32]] zeroinitializer, align 16
+ at a = common dso_local local_unnamed_addr global [1 x [10 x i32]] zeroinitializer, align 16
+ at c = common dso_local local_unnamed_addr global i32 0, align 4
+ at b = common dso_local local_unnamed_addr global [1 x [7 x i32]] zeroinitializer, align 16
; Function Attrs: norecurse nounwind uwtable
-define void @fn1() local_unnamed_addr #0 {
+define dso_local void @fn1() local_unnamed_addr #0 {
; CHECK-LABEL: fn1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: movslq {{.*}}(%rip), %rax
@@ -31,7 +31,7 @@ entry:
}
; Function Attrs: norecurse nounwind uwtable
-define i32 @main() local_unnamed_addr #0 {
+define dso_local i32 @main() local_unnamed_addr #0 {
; CHECK-LABEL: main:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: movslq {{.*}}(%rip), %rax
diff --git a/llvm/test/CodeGen/X86/pr35761.ll b/llvm/test/CodeGen/X86/pr35761.ll
index 0bf81bff841f..aaab027282a9 100644
--- a/llvm/test/CodeGen/X86/pr35761.ll
+++ b/llvm/test/CodeGen/X86/pr35761.ll
@@ -1,11 +1,11 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=x86_64-unknown-linux %s -o - | FileCheck %s
- at x = global i8 0, align 1
- at y = global i32 0, align 4
- at z = global i24 0, align 4
+ at x = dso_local global i8 0, align 1
+ at y = dso_local global i32 0, align 4
+ at z = dso_local global i24 0, align 4
-define void @PR35761(i32 %call) {
+define dso_local void @PR35761(i32 %call) {
; CHECK-LABEL: PR35761:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: movzbl {{.*}}(%rip), %eax
diff --git a/llvm/test/CodeGen/X86/pr35763.ll b/llvm/test/CodeGen/X86/pr35763.ll
index f99cbcdeaa9a..6b67d04ad772 100644
--- a/llvm/test/CodeGen/X86/pr35763.ll
+++ b/llvm/test/CodeGen/X86/pr35763.ll
@@ -3,11 +3,11 @@
%struct.S = type <{ i16, i24, [5 x i8], i8, i16, [2 x i8] }>
- at z = global { i16, i8, i8, i8, i8, i8, i8, i8, i8, i8, [5 x i8] } { i16 -724, i8 94, i8 -18, i8 5, i8 undef, i8 96, i8 104, i8 -24, i8 10, i8 0, [5 x i8] undef }, align 8
- at tf_3_var_136 = global i64 0, align 8
+ at z = dso_local global { i16, i8, i8, i8, i8, i8, i8, i8, i8, i8, [5 x i8] } { i16 -724, i8 94, i8 -18, i8 5, i8 undef, i8 96, i8 104, i8 -24, i8 10, i8 0, [5 x i8] undef }, align 8
+ at tf_3_var_136 = dso_local global i64 0, align 8
@.str = private unnamed_addr constant [6 x i8] c"%llu\0A\00", align 1
-define void @PR35763() {
+define dso_local void @PR35763() {
; CHECK-LABEL: PR35763:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: movl {{.*}}(%rip), %eax
diff --git a/llvm/test/CodeGen/X86/pr35765.ll b/llvm/test/CodeGen/X86/pr35765.ll
index 1c6035fdc110..b421dcc6095e 100644
--- a/llvm/test/CodeGen/X86/pr35765.ll
+++ b/llvm/test/CodeGen/X86/pr35765.ll
@@ -1,12 +1,12 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=x86_64-unknown-linux-gnu %s -o - | FileCheck %s
- at ll = local_unnamed_addr global i64 0, align 8
- at x = local_unnamed_addr global i64 2651237805702985558, align 8
- at s1 = local_unnamed_addr global { i8, i8 } { i8 123, i8 5 }, align 2
- at s2 = local_unnamed_addr global { i8, i8 } { i8 -122, i8 3 }, align 2
+ at ll = dso_local local_unnamed_addr global i64 0, align 8
+ at x = dso_local local_unnamed_addr global i64 2651237805702985558, align 8
+ at s1 = dso_local local_unnamed_addr global { i8, i8 } { i8 123, i8 5 }, align 2
+ at s2 = dso_local local_unnamed_addr global { i8, i8 } { i8 -122, i8 3 }, align 2
-define void @PR35765() {
+define dso_local void @PR35765() {
; CHECK-LABEL: PR35765:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: movb {{.*}}(%rip), %cl
diff --git a/llvm/test/CodeGen/X86/pr36312.ll b/llvm/test/CodeGen/X86/pr36312.ll
index 64048511ac7d..4481b734421b 100644
--- a/llvm/test/CodeGen/X86/pr36312.ll
+++ b/llvm/test/CodeGen/X86/pr36312.ll
@@ -3,10 +3,10 @@
%struct.anon = type { i32, i32 }
- at c = common global %struct.anon zeroinitializer, align 4
- at d = local_unnamed_addr global %struct.anon* @c, align 8
- at a = common local_unnamed_addr global i32 0, align 4
- at b = common local_unnamed_addr global i32 0, align 4
+ at c = common dso_local global %struct.anon zeroinitializer, align 4
+ at d = dso_local local_unnamed_addr global %struct.anon* @c, align 8
+ at a = common dso_local local_unnamed_addr global i32 0, align 4
+ at b = common dso_local local_unnamed_addr global i32 0, align 4
; Function Attrs: norecurse nounwind uwtable
define void @g() local_unnamed_addr #0 {
diff --git a/llvm/test/CodeGen/X86/pr37826.ll b/llvm/test/CodeGen/X86/pr37826.ll
index ee93d5f96600..bd31bf4d88d0 100644
--- a/llvm/test/CodeGen/X86/pr37826.ll
+++ b/llvm/test/CodeGen/X86/pr37826.ll
@@ -4,13 +4,13 @@
; When compiled and run this should print zero.
- at c = common local_unnamed_addr global i32 0, align 4
- at f = common local_unnamed_addr global i32 0, align 4
- at e = common local_unnamed_addr global i32 0, align 4
+ at c = common dso_local local_unnamed_addr global i32 0, align 4
+ at f = common dso_local local_unnamed_addr global i32 0, align 4
+ at e = common dso_local local_unnamed_addr global i32 0, align 4
@.str.1 = private unnamed_addr constant [4 x i8] c"%d\0A\00", align 1
; We should only see a single store to f (a bytes store to f+3).
-define void @k(i32 %l) {
+define dso_local void @k(i32 %l) {
; CHECK-LABEL: k:
; CHECK: # %bb.0:
; CHECK-NEXT: movl {{.*}}(%rip), %eax
@@ -38,7 +38,7 @@ define void @k(i32 %l) {
declare i32 @printf(i8* nocapture readonly, ...)
-define i32 @main() {
+define dso_local i32 @main() {
; CHECK-LABEL: main:
; CHECK: # %bb.0:
; CHECK-NEXT: pushq %rax
diff --git a/llvm/test/CodeGen/X86/pr38217.ll b/llvm/test/CodeGen/X86/pr38217.ll
index 951d4645d5d0..404855b6222f 100644
--- a/llvm/test/CodeGen/X86/pr38217.ll
+++ b/llvm/test/CodeGen/X86/pr38217.ll
@@ -1,9 +1,9 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=x86_64-unknown-unknown | FileCheck %s
- at _ZL11DIGIT_TABLE = constant [201 x i8] c"00010203040506070809101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899\00", align 16
+ at _ZL11DIGIT_TABLE = dso_local constant [201 x i8] c"00010203040506070809101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899\00", align 16
-define void @_Z12d2s_bufferedmPc(i64, i8* nocapture) {
+define dso_local void @_Z12d2s_bufferedmPc(i64, i8* nocapture) {
; CHECK-LABEL: _Z12d2s_bufferedmPc:
; CHECK: # %bb.0:
; CHECK-NEXT: cmpq $10000, %rdi # imm = 0x2710
diff --git a/llvm/test/CodeGen/X86/pr38803.ll b/llvm/test/CodeGen/X86/pr38803.ll
index a2fc19e0cde9..a9f094a2ee6c 100644
--- a/llvm/test/CodeGen/X86/pr38803.ll
+++ b/llvm/test/CodeGen/X86/pr38803.ll
@@ -1,11 +1,11 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mcpu=skylake-avx512 -mtriple=x86_64-unknown-unknown | FileCheck %s
- at b = local_unnamed_addr global i32 0, align 4
- at c = local_unnamed_addr global i32 0, align 4
- at d = local_unnamed_addr global float 0.000000e+00, align 4
+ at b = dso_local local_unnamed_addr global i32 0, align 4
+ at c = dso_local local_unnamed_addr global i32 0, align 4
+ at d = dso_local local_unnamed_addr global float 0.000000e+00, align 4
-define float @_Z3fn2v() {
+define dso_local float @_Z3fn2v() {
; CHECK-LABEL: _Z3fn2v:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: pushq %rax
diff --git a/llvm/test/CodeGen/X86/pr38865.ll b/llvm/test/CodeGen/X86/pr38865.ll
index 489485274cdb..777842cc7d4d 100644
--- a/llvm/test/CodeGen/X86/pr38865.ll
+++ b/llvm/test/CodeGen/X86/pr38865.ll
@@ -6,9 +6,9 @@ target triple = "x86_64-unknown-linux-gnux32"
%struct.a = type { [65 x i32] }
- at c = global %struct.a zeroinitializer, align 4
+ at c = dso_local global %struct.a zeroinitializer, align 4
-define void @e() nounwind {
+define dso_local void @e() nounwind {
; CHECK-LABEL: e:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: pushq %rbx # encoding: [0x53]
diff --git a/llvm/test/CodeGen/X86/pr43866.ll b/llvm/test/CodeGen/X86/pr43866.ll
index a430975c47d4..8a012d74bce6 100644
--- a/llvm/test/CodeGen/X86/pr43866.ll
+++ b/llvm/test/CodeGen/X86/pr43866.ll
@@ -1,9 +1,9 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=avx | FileCheck %s
- at v2_0 = global <2 x i32> zeroinitializer, align 8
+ at v2_0 = dso_local global <2 x i32> zeroinitializer, align 8
-define void @test() {
+define dso_local void @test() {
; CHECK-LABEL: test:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: pushq %rbp
diff --git a/llvm/test/CodeGen/X86/rd-mod-wr-eflags.ll b/llvm/test/CodeGen/X86/rd-mod-wr-eflags.ll
index e9210f89257c..ae520e4ebd8e 100644
--- a/llvm/test/CodeGen/X86/rd-mod-wr-eflags.ll
+++ b/llvm/test/CodeGen/X86/rd-mod-wr-eflags.ll
@@ -3,7 +3,7 @@
%struct.obj = type { i64 }
-define void @_Z7releaseP3obj(%struct.obj* nocapture %o) nounwind uwtable ssp {
+define dso_local void @_Z7releaseP3obj(%struct.obj* nocapture %o) nounwind uwtable ssp {
; CHECK-LABEL: _Z7releaseP3obj:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: decq (%rdi)
@@ -29,12 +29,12 @@ return: ; preds = %entry, %if.end
ret void
}
- at c = common global i64 0, align 8
- at a = common global i32 0, align 4
+ at c = common dso_local global i64 0, align 8
+ at a = common dso_local global i32 0, align 4
@.str = private unnamed_addr constant [5 x i8] c"%ld\0A\00", align 1
- at b = common global i32 0, align 4
+ at b = common dso_local global i32 0, align 4
-define i32 @test() nounwind uwtable ssp {
+define dso_local i32 @test() nounwind uwtable ssp {
; CHECK-LABEL: test:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: pushq %rax
@@ -63,7 +63,7 @@ store i32 %lor.ext.i, i32* @a, align 4
ret i32 0
}
-define i32 @test2() nounwind uwtable ssp {
+define dso_local i32 @test2() nounwind uwtable ssp {
; CHECK-LABEL: test2:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: pushq %rax
@@ -100,7 +100,7 @@ declare dso_local void @free(i8* nocapture) nounwind
declare dso_local void @other(%struct.obj2* ) nounwind;
-define void @example_dec(%struct.obj2* %o) nounwind uwtable ssp {
+define dso_local void @example_dec(%struct.obj2* %o) nounwind uwtable ssp {
; 64 bit dec
; CHECK-LABEL: example_dec:
; CHECK: # %bb.0: # %entry
@@ -162,7 +162,7 @@ return: ; preds = %if.end4, %if.end, %
ret void
}
-define void @example_inc(%struct.obj2* %o) nounwind uwtable ssp {
+define dso_local void @example_inc(%struct.obj2* %o) nounwind uwtable ssp {
; 64 bit inc
; CHECK-LABEL: example_inc:
; CHECK: # %bb.0: # %entry
@@ -228,7 +228,7 @@ return:
; rdar://11236106
@foo = external dso_local global i64*, align 8
-define void @test3() nounwind ssp {
+define dso_local void @test3() nounwind ssp {
; CHECK-LABEL: test3:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: movq {{.*}}(%rip), %rax
@@ -265,7 +265,7 @@ declare dso_local void @baz()
@y = external dso_local global i32, align 4
@z = external dso_local global i32, align 4
-define void @test4() nounwind uwtable ssp {
+define dso_local void @test4() nounwind uwtable ssp {
; CHECK-LABEL: test4:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xorl %eax, %eax
diff --git a/llvm/test/CodeGen/X86/sad.ll b/llvm/test/CodeGen/X86/sad.ll
index ef26c84bdf5e..bf04403694e1 100644
--- a/llvm/test/CodeGen/X86/sad.ll
+++ b/llvm/test/CodeGen/X86/sad.ll
@@ -5,10 +5,10 @@
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512f | FileCheck %s --check-prefixes=AVX,AVX512,AVX512F
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512bw | FileCheck %s --check-prefixes=AVX,AVX512,AVX512BW
- at a = global [1024 x i8] zeroinitializer, align 16
- at b = global [1024 x i8] zeroinitializer, align 16
+ at a = dso_local global [1024 x i8] zeroinitializer, align 16
+ at b = dso_local global [1024 x i8] zeroinitializer, align 16
-define i32 @sad_16i8() nounwind {
+define dso_local i32 @sad_16i8() nounwind {
; SSE2-LABEL: sad_16i8:
; SSE2: # %bb.0: # %entry
; SSE2-NEXT: pxor %xmm0, %xmm0
@@ -147,7 +147,7 @@ middle.block:
ret i32 %12
}
-define i32 @sad_32i8() nounwind {
+define dso_local i32 @sad_32i8() nounwind {
; SSE2-LABEL: sad_32i8:
; SSE2: # %bb.0: # %entry
; SSE2-NEXT: pxor %xmm0, %xmm0
@@ -306,7 +306,7 @@ middle.block:
ret i32 %12
}
-define i32 @sad_avx64i8() nounwind {
+define dso_local i32 @sad_avx64i8() nounwind {
; SSE2-LABEL: sad_avx64i8:
; SSE2: # %bb.0: # %entry
; SSE2-NEXT: pxor %xmm4, %xmm4
@@ -539,7 +539,7 @@ middle.block:
ret i32 %12
}
-define i32 @sad_2i8() nounwind {
+define dso_local i32 @sad_2i8() nounwind {
; SSE2-LABEL: sad_2i8:
; SSE2: # %bb.0: # %entry
; SSE2-NEXT: pxor %xmm0, %xmm0
@@ -613,7 +613,7 @@ middle.block:
ret i32 %12
}
-define i32 @sad_4i8() nounwind {
+define dso_local i32 @sad_4i8() nounwind {
; SSE2-LABEL: sad_4i8:
; SSE2: # %bb.0: # %entry
; SSE2-NEXT: pxor %xmm0, %xmm0
@@ -688,7 +688,7 @@ middle.block:
}
-define i32 @sad_nonloop_4i8(<4 x i8>* nocapture readonly %p, i64, <4 x i8>* nocapture readonly %q) local_unnamed_addr #0 {
+define dso_local i32 @sad_nonloop_4i8(<4 x i8>* nocapture readonly %p, i64, <4 x i8>* nocapture readonly %q) local_unnamed_addr #0 {
; SSE2-LABEL: sad_nonloop_4i8:
; SSE2: # %bb.0:
; SSE2-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero
@@ -720,7 +720,7 @@ define i32 @sad_nonloop_4i8(<4 x i8>* nocapture readonly %p, i64, <4 x i8>* noca
ret i32 %sum
}
-define i32 @sad_nonloop_8i8(<8 x i8>* nocapture readonly %p, i64, <8 x i8>* nocapture readonly %q) local_unnamed_addr #0 {
+define dso_local i32 @sad_nonloop_8i8(<8 x i8>* nocapture readonly %p, i64, <8 x i8>* nocapture readonly %q) local_unnamed_addr #0 {
; SSE2-LABEL: sad_nonloop_8i8:
; SSE2: # %bb.0:
; SSE2-NEXT: movq {{.*#+}} xmm0 = mem[0],zero
@@ -754,7 +754,7 @@ define i32 @sad_nonloop_8i8(<8 x i8>* nocapture readonly %p, i64, <8 x i8>* noca
ret i32 %sum
}
-define i32 @sad_nonloop_16i8(<16 x i8>* nocapture readonly %p, i64, <16 x i8>* nocapture readonly %q) local_unnamed_addr #0 {
+define dso_local i32 @sad_nonloop_16i8(<16 x i8>* nocapture readonly %p, i64, <16 x i8>* nocapture readonly %q) local_unnamed_addr #0 {
; SSE2-LABEL: sad_nonloop_16i8:
; SSE2: # %bb.0:
; SSE2-NEXT: movdqu (%rdi), %xmm0
@@ -793,7 +793,7 @@ define i32 @sad_nonloop_16i8(<16 x i8>* nocapture readonly %p, i64, <16 x i8>* n
ret i32 %sum
}
-define i32 @sad_nonloop_32i8(<32 x i8>* nocapture readonly %p, i64, <32 x i8>* nocapture readonly %q) local_unnamed_addr #0 {
+define dso_local i32 @sad_nonloop_32i8(<32 x i8>* nocapture readonly %p, i64, <32 x i8>* nocapture readonly %q) local_unnamed_addr #0 {
; SSE2-LABEL: sad_nonloop_32i8:
; SSE2: # %bb.0:
; SSE2-NEXT: movdqu (%rdx), %xmm0
@@ -865,7 +865,7 @@ define i32 @sad_nonloop_32i8(<32 x i8>* nocapture readonly %p, i64, <32 x i8>* n
ret i32 %sum
}
-define i32 @sad_nonloop_64i8(<64 x i8>* nocapture readonly %p, i64, <64 x i8>* nocapture readonly %q) local_unnamed_addr #0 {
+define dso_local i32 @sad_nonloop_64i8(<64 x i8>* nocapture readonly %p, i64, <64 x i8>* nocapture readonly %q) local_unnamed_addr #0 {
; SSE2-LABEL: sad_nonloop_64i8:
; SSE2: # %bb.0:
; SSE2-NEXT: movdqu (%rdx), %xmm0
@@ -976,7 +976,7 @@ define i32 @sad_nonloop_64i8(<64 x i8>* nocapture readonly %p, i64, <64 x i8>* n
; This contains an unrolled sad loop with a non-zero initial value.
; DAGCombiner reassociation previously rewrote the adds to move the constant vector further down the tree. This resulted in the vector-reduction flag being lost.
-define i32 @sad_unroll_nonzero_initial(<16 x i8>* %arg, <16 x i8>* %arg1, <16 x i8>* %arg2, <16 x i8>* %arg3) {
+define dso_local i32 @sad_unroll_nonzero_initial(<16 x i8>* %arg, <16 x i8>* %arg1, <16 x i8>* %arg2, <16 x i8>* %arg3) {
; SSE2-LABEL: sad_unroll_nonzero_initial:
; SSE2: # %bb.0: # %bb
; SSE2-NEXT: movdqu (%rdi), %xmm0
@@ -1041,7 +1041,7 @@ bb:
; This test contains two absolute
diff erence patterns joined by an add. The result of that add is then reduced to a single element.
; SelectionDAGBuilder should tag the joining add as a vector reduction. We neeed to recognize that both sides can use psadbw.
-define i32 @sad_double_reduction(<16 x i8>* %arg, <16 x i8>* %arg1, <16 x i8>* %arg2, <16 x i8>* %arg3) {
+define dso_local i32 @sad_double_reduction(<16 x i8>* %arg, <16 x i8>* %arg1, <16 x i8>* %arg2, <16 x i8>* %arg3) {
; SSE2-LABEL: sad_double_reduction:
; SSE2: # %bb.0: # %bb
; SSE2-NEXT: movdqu (%rdi), %xmm0
diff --git a/llvm/test/CodeGen/X86/shift-combine.ll b/llvm/test/CodeGen/X86/shift-combine.ll
index 1582544b507c..b40754b82300 100644
--- a/llvm/test/CodeGen/X86/shift-combine.ll
+++ b/llvm/test/CodeGen/X86/shift-combine.ll
@@ -2,9 +2,9 @@
; RUN: llc -mtriple=i686-unknown < %s | FileCheck %s --check-prefix=X32
; RUN: llc -mtriple=x86_64-unknown < %s | FileCheck %s --check-prefix=X64
- at array = weak global [4 x i32] zeroinitializer
+ at array = weak dso_local global [4 x i32] zeroinitializer
-define i32 @test_lshr_and(i32 %x) {
+define dso_local i32 @test_lshr_and(i32 %x) {
; X32-LABEL: test_lshr_and:
; X32: # %bb.0:
; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
@@ -26,7 +26,7 @@ define i32 @test_lshr_and(i32 %x) {
ret i32 %tmp5
}
-define i32* @test_exact1(i32 %a, i32 %b, i32* %x) {
+define dso_local i32* @test_exact1(i32 %a, i32 %b, i32* %x) {
; X32-LABEL: test_exact1:
; X32: # %bb.0:
; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
@@ -48,7 +48,7 @@ define i32* @test_exact1(i32 %a, i32 %b, i32* %x) {
ret i32* %gep
}
-define i32* @test_exact2(i32 %a, i32 %b, i32* %x) {
+define dso_local i32* @test_exact2(i32 %a, i32 %b, i32* %x) {
; X32-LABEL: test_exact2:
; X32: # %bb.0:
; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
@@ -70,7 +70,7 @@ define i32* @test_exact2(i32 %a, i32 %b, i32* %x) {
ret i32* %gep
}
-define i32* @test_exact3(i32 %a, i32 %b, i32* %x) {
+define dso_local i32* @test_exact3(i32 %a, i32 %b, i32* %x) {
; X32-LABEL: test_exact3:
; X32: # %bb.0:
; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
@@ -91,7 +91,7 @@ define i32* @test_exact3(i32 %a, i32 %b, i32* %x) {
ret i32* %gep
}
-define i32* @test_exact4(i32 %a, i32 %b, i32* %x) {
+define dso_local i32* @test_exact4(i32 %a, i32 %b, i32* %x) {
; X32-LABEL: test_exact4:
; X32: # %bb.0:
; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
@@ -113,7 +113,7 @@ define i32* @test_exact4(i32 %a, i32 %b, i32* %x) {
ret i32* %gep
}
-define i32* @test_exact5(i32 %a, i32 %b, i32* %x) {
+define dso_local i32* @test_exact5(i32 %a, i32 %b, i32* %x) {
; X32-LABEL: test_exact5:
; X32: # %bb.0:
; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
@@ -135,7 +135,7 @@ define i32* @test_exact5(i32 %a, i32 %b, i32* %x) {
ret i32* %gep
}
-define i32* @test_exact6(i32 %a, i32 %b, i32* %x) {
+define dso_local i32* @test_exact6(i32 %a, i32 %b, i32* %x) {
; X32-LABEL: test_exact6:
; X32: # %bb.0:
; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
@@ -304,7 +304,7 @@ define i64 @ashr_add_shl_mismatch_shifts2(i64 %r) nounwind {
ret i64 %conv1
}
-define i32 @ashr_add_shl_i32_i8_extra_use1(i32 %r, i32* %p) nounwind {
+define dso_local i32 @ashr_add_shl_i32_i8_extra_use1(i32 %r, i32* %p) nounwind {
; X32-LABEL: ashr_add_shl_i32_i8_extra_use1:
; X32: # %bb.0:
; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx
@@ -330,7 +330,7 @@ define i32 @ashr_add_shl_i32_i8_extra_use1(i32 %r, i32* %p) nounwind {
ret i32 %conv1
}
-define i32 @ashr_add_shl_i32_i8_extra_use2(i32 %r, i32* %p) nounwind {
+define dso_local i32 @ashr_add_shl_i32_i8_extra_use2(i32 %r, i32* %p) nounwind {
; X32-LABEL: ashr_add_shl_i32_i8_extra_use2:
; X32: # %bb.0:
; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx
@@ -356,7 +356,7 @@ define i32 @ashr_add_shl_i32_i8_extra_use2(i32 %r, i32* %p) nounwind {
ret i32 %conv1
}
-define i32 @ashr_add_shl_i32_i8_extra_use3(i32 %r, i32* %p1, i32* %p2) nounwind {
+define dso_local i32 @ashr_add_shl_i32_i8_extra_use3(i32 %r, i32* %p1, i32* %p2) nounwind {
; X32-LABEL: ashr_add_shl_i32_i8_extra_use3:
; X32: # %bb.0:
; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx
@@ -388,7 +388,7 @@ define i32 @ashr_add_shl_i32_i8_extra_use3(i32 %r, i32* %p1, i32* %p2) nounwind
%"class.QPainterPath" = type { double, double, i32 }
-define void @PR42880(i32 %t0) {
+define dso_local void @PR42880(i32 %t0) {
; X32-LABEL: PR42880:
; X32: # %bb.0:
; X32-NEXT: xorl %eax, %eax
diff --git a/llvm/test/CodeGen/X86/shrink-compare-pgso.ll b/llvm/test/CodeGen/X86/shrink-compare-pgso.ll
index 8f1bbdb0bf4e..ede2b2440a4f 100644
--- a/llvm/test/CodeGen/X86/shrink-compare-pgso.ll
+++ b/llvm/test/CodeGen/X86/shrink-compare-pgso.ll
@@ -3,7 +3,7 @@
declare dso_local void @bar()
-define void @test1(i32* nocapture %X) nounwind !prof !14 {
+define dso_local void @test1(i32* nocapture %X) nounwind !prof !14 {
; CHECK-LABEL: test1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: cmpb $47, (%rdi)
@@ -24,7 +24,7 @@ if.end:
ret void
}
-define void @test2(i32 %X) nounwind !prof !14 {
+define dso_local void @test2(i32 %X) nounwind !prof !14 {
; CHECK-LABEL: test2:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: cmpb $47, %dil
@@ -44,7 +44,7 @@ if.end:
ret void
}
-define void @test3(i32 %X) nounwind !prof !14 {
+define dso_local void @test3(i32 %X) nounwind !prof !14 {
; CHECK-LABEL: test3:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: cmpb $-1, %dil
@@ -92,10 +92,10 @@ lor.end: ; preds = %lor.rhs, %entry
ret i1 %p
}
- at x = global { i8, i8, i8, i8, i8, i8, i8, i8 } { i8 1, i8 0, i8 0, i8 0, i8 1, i8 0, i8 0, i8 1 }, align 4
+ at x = dso_local global { i8, i8, i8, i8, i8, i8, i8, i8 } { i8 1, i8 0, i8 0, i8 0, i8 1, i8 0, i8 0, i8 1 }, align 4
; PR16551
-define void @test5(i32 %X) nounwind !prof !14 {
+define dso_local void @test5(i32 %X) nounwind !prof !14 {
; CHECK-LABEL: test5:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: movzbl x+{{.*}}(%rip), %eax
@@ -121,7 +121,7 @@ if.end:
ret void
}
-define void @test2_1(i32 %X) nounwind !prof !14 {
+define dso_local void @test2_1(i32 %X) nounwind !prof !14 {
; CHECK-LABEL: test2_1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: movzbl %dil, %eax
@@ -142,7 +142,7 @@ if.end:
ret void
}
-define void @test_sext_i8_icmp_1(i8 %x) nounwind !prof !14 {
+define dso_local void @test_sext_i8_icmp_1(i8 %x) nounwind !prof !14 {
; CHECK-LABEL: test_sext_i8_icmp_1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: cmpb $1, %dil
@@ -162,7 +162,7 @@ if.end:
ret void
}
-define void @test_sext_i8_icmp_47(i8 %x) nounwind !prof !14 {
+define dso_local void @test_sext_i8_icmp_47(i8 %x) nounwind !prof !14 {
; CHECK-LABEL: test_sext_i8_icmp_47:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: cmpb $47, %dil
@@ -182,7 +182,7 @@ if.end:
ret void
}
-define void @test_sext_i8_icmp_127(i8 %x) nounwind !prof !14 {
+define dso_local void @test_sext_i8_icmp_127(i8 %x) nounwind !prof !14 {
; CHECK-LABEL: test_sext_i8_icmp_127:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: cmpb $127, %dil
@@ -202,7 +202,7 @@ if.end:
ret void
}
-define void @test_sext_i8_icmp_neg1(i8 %x) nounwind !prof !14 {
+define dso_local void @test_sext_i8_icmp_neg1(i8 %x) nounwind !prof !14 {
; CHECK-LABEL: test_sext_i8_icmp_neg1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: cmpb $-1, %dil
@@ -222,7 +222,7 @@ if.end:
ret void
}
-define void @test_sext_i8_icmp_neg2(i8 %x) nounwind !prof !14 {
+define dso_local void @test_sext_i8_icmp_neg2(i8 %x) nounwind !prof !14 {
; CHECK-LABEL: test_sext_i8_icmp_neg2:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: cmpb $-2, %dil
@@ -242,7 +242,7 @@ if.end:
ret void
}
-define void @test_sext_i8_icmp_neg127(i8 %x) nounwind !prof !14 {
+define dso_local void @test_sext_i8_icmp_neg127(i8 %x) nounwind !prof !14 {
; CHECK-LABEL: test_sext_i8_icmp_neg127:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: cmpb $-127, %dil
@@ -262,7 +262,7 @@ if.end:
ret void
}
-define void @test_sext_i8_icmp_neg128(i8 %x) nounwind !prof !14 {
+define dso_local void @test_sext_i8_icmp_neg128(i8 %x) nounwind !prof !14 {
; CHECK-LABEL: test_sext_i8_icmp_neg128:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: cmpb $-128, %dil
@@ -282,7 +282,7 @@ if.end:
ret void
}
-define void @test_sext_i8_icmp_255(i8 %x) nounwind !prof !14 {
+define dso_local void @test_sext_i8_icmp_255(i8 %x) nounwind !prof !14 {
; CHECK-LABEL: test_sext_i8_icmp_255:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: movb $1, %al
diff --git a/llvm/test/CodeGen/X86/shrink-compare.ll b/llvm/test/CodeGen/X86/shrink-compare.ll
index 1929c01c5904..5da8e4015f62 100644
--- a/llvm/test/CodeGen/X86/shrink-compare.ll
+++ b/llvm/test/CodeGen/X86/shrink-compare.ll
@@ -3,7 +3,7 @@
declare dso_local void @bar()
-define void @test1(i32* nocapture %X) nounwind minsize {
+define dso_local void @test1(i32* nocapture %X) nounwind minsize {
; CHECK-LABEL: test1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: cmpb $47, (%rdi)
@@ -24,7 +24,7 @@ if.end:
ret void
}
-define void @test2(i32 %X) nounwind minsize {
+define dso_local void @test2(i32 %X) nounwind minsize {
; CHECK-LABEL: test2:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: cmpb $47, %dil
@@ -44,7 +44,7 @@ if.end:
ret void
}
-define void @test3(i32 %X) nounwind minsize {
+define dso_local void @test3(i32 %X) nounwind minsize {
; CHECK-LABEL: test3:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: cmpb $-1, %dil
@@ -92,10 +92,10 @@ lor.end: ; preds = %lor.rhs, %entry
ret i1 %p
}
- at x = global { i8, i8, i8, i8, i8, i8, i8, i8 } { i8 1, i8 0, i8 0, i8 0, i8 1, i8 0, i8 0, i8 1 }, align 4
+ at x = dso_local global { i8, i8, i8, i8, i8, i8, i8, i8 } { i8 1, i8 0, i8 0, i8 0, i8 1, i8 0, i8 0, i8 1 }, align 4
; PR16551
-define void @test5(i32 %X) nounwind minsize {
+define dso_local void @test5(i32 %X) nounwind minsize {
; CHECK-LABEL: test5:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: movzbl x+{{.*}}(%rip), %eax
@@ -121,7 +121,7 @@ if.end:
ret void
}
-define void @test2_1(i32 %X) nounwind minsize {
+define dso_local void @test2_1(i32 %X) nounwind minsize {
; CHECK-LABEL: test2_1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: movzbl %dil, %eax
@@ -142,7 +142,7 @@ if.end:
ret void
}
-define void @test_sext_i8_icmp_1(i8 %x) nounwind minsize {
+define dso_local void @test_sext_i8_icmp_1(i8 %x) nounwind minsize {
; CHECK-LABEL: test_sext_i8_icmp_1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: cmpb $1, %dil
@@ -162,7 +162,7 @@ if.end:
ret void
}
-define void @test_sext_i8_icmp_47(i8 %x) nounwind minsize {
+define dso_local void @test_sext_i8_icmp_47(i8 %x) nounwind minsize {
; CHECK-LABEL: test_sext_i8_icmp_47:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: cmpb $47, %dil
@@ -182,7 +182,7 @@ if.end:
ret void
}
-define void @test_sext_i8_icmp_127(i8 %x) nounwind minsize {
+define dso_local void @test_sext_i8_icmp_127(i8 %x) nounwind minsize {
; CHECK-LABEL: test_sext_i8_icmp_127:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: cmpb $127, %dil
@@ -202,7 +202,7 @@ if.end:
ret void
}
-define void @test_sext_i8_icmp_neg1(i8 %x) nounwind minsize {
+define dso_local void @test_sext_i8_icmp_neg1(i8 %x) nounwind minsize {
; CHECK-LABEL: test_sext_i8_icmp_neg1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: cmpb $-1, %dil
@@ -222,7 +222,7 @@ if.end:
ret void
}
-define void @test_sext_i8_icmp_neg2(i8 %x) nounwind minsize {
+define dso_local void @test_sext_i8_icmp_neg2(i8 %x) nounwind minsize {
; CHECK-LABEL: test_sext_i8_icmp_neg2:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: cmpb $-2, %dil
@@ -242,7 +242,7 @@ if.end:
ret void
}
-define void @test_sext_i8_icmp_neg127(i8 %x) nounwind minsize {
+define dso_local void @test_sext_i8_icmp_neg127(i8 %x) nounwind minsize {
; CHECK-LABEL: test_sext_i8_icmp_neg127:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: cmpb $-127, %dil
@@ -262,7 +262,7 @@ if.end:
ret void
}
-define void @test_sext_i8_icmp_neg128(i8 %x) nounwind minsize {
+define dso_local void @test_sext_i8_icmp_neg128(i8 %x) nounwind minsize {
; CHECK-LABEL: test_sext_i8_icmp_neg128:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: cmpb $-128, %dil
@@ -282,7 +282,7 @@ if.end:
ret void
}
-define void @test_sext_i8_icmp_255(i8 %x) nounwind minsize {
+define dso_local void @test_sext_i8_icmp_255(i8 %x) nounwind minsize {
; CHECK-LABEL: test_sext_i8_icmp_255:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: movb $1, %al
diff --git a/llvm/test/CodeGen/X86/sibcall.ll b/llvm/test/CodeGen/X86/sibcall.ll
index de2509cc4c1c..0effa4551e58 100644
--- a/llvm/test/CodeGen/X86/sibcall.ll
+++ b/llvm/test/CodeGen/X86/sibcall.ll
@@ -3,7 +3,7 @@
; RUN: llc -verify-machineinstrs < %s -mtriple=x86_64-linux -mcpu=core2 -mattr=+sse2 | FileCheck %s --check-prefix=X64
; RUN: llc -verify-machineinstrs < %s -mtriple=x86_64-linux-gnux32 -mcpu=core2 -mattr=+sse2 | FileCheck %s --check-prefix=X32
-define void @t1(i32 %x) nounwind ssp {
+define dso_local void @t1(i32 %x) nounwind ssp {
; X86-LABEL: t1:
; X86: # %bb.0:
; X86-NEXT: jmp foo # TAILCALL
@@ -21,7 +21,7 @@ define void @t1(i32 %x) nounwind ssp {
declare dso_local void @foo()
-define void @t2() nounwind ssp {
+define dso_local void @t2() nounwind ssp {
; X86-LABEL: t2:
; X86: # %bb.0:
; X86-NEXT: jmp foo2 # TAILCALL
@@ -39,7 +39,7 @@ define void @t2() nounwind ssp {
declare dso_local i32 @foo2()
-define void @t3() nounwind ssp {
+define dso_local void @t3() nounwind ssp {
; X86-LABEL: t3:
; X86: # %bb.0:
; X86-NEXT: jmp foo3 # TAILCALL
@@ -57,7 +57,7 @@ define void @t3() nounwind ssp {
declare dso_local i32 @foo3()
-define void @t4(void (i32)* nocapture %x) nounwind ssp {
+define dso_local void @t4(void (i32)* nocapture %x) nounwind ssp {
; X86-LABEL: t4:
; X86: # %bb.0:
; X86-NEXT: subl $12, %esp
@@ -81,7 +81,7 @@ define void @t4(void (i32)* nocapture %x) nounwind ssp {
ret void
}
-define void @t5(void ()* nocapture %x) nounwind ssp {
+define dso_local void @t5(void ()* nocapture %x) nounwind ssp {
; X86-LABEL: t5:
; X86: # %bb.0:
; X86-NEXT: jmpl *{{[0-9]+}}(%esp) # TAILCALL
@@ -100,7 +100,7 @@ define void @t5(void ()* nocapture %x) nounwind ssp {
; Basically the same test as t5, except pass the function pointer on the stack
; for x86_64.
-define void @t5_x64(i32, i32, i32, i32, i32, i32, void ()* nocapture %x) nounwind ssp {
+define dso_local void @t5_x64(i32, i32, i32, i32, i32, i32, void ()* nocapture %x) nounwind ssp {
; X86-LABEL: t5_x64:
; X86: # %bb.0:
; X86-NEXT: jmpl *{{[0-9]+}}(%esp) # TAILCALL
@@ -118,7 +118,7 @@ define void @t5_x64(i32, i32, i32, i32, i32, i32, void ()* nocapture %x) nounwin
}
-define i32 @t6(i32 %x) nounwind ssp {
+define dso_local i32 @t6(i32 %x) nounwind ssp {
; X86-LABEL: t6:
; X86: # %bb.0:
; X86-NEXT: subl $12, %esp
@@ -169,7 +169,7 @@ bb1:
declare dso_local i32 @bar(i32)
-define i32 @t7(i32 %a, i32 %b, i32 %c) nounwind ssp {
+define dso_local i32 @t7(i32 %a, i32 %b, i32 %c) nounwind ssp {
; X86-LABEL: t7:
; X86: # %bb.0:
; X86-NEXT: jmp bar2 # TAILCALL
@@ -232,7 +232,7 @@ entry:
ret i16 %1
}
-define void @t10() nounwind ssp {
+define dso_local void @t10() nounwind ssp {
; X86-LABEL: t10:
; X86: # %bb.0: # %entry
; X86-NEXT: subl $12, %esp
@@ -257,7 +257,7 @@ declare dso_local i32 @foo4()
; In 32-bit mode, it's emitting a bunch of dead loads that are not being
; eliminated currently.
-define i32 @t11(i32 %x, i32 %y, i32 %z.0, i32 %z.1, i32 %z.2) nounwind ssp {
+define dso_local i32 @t11(i32 %x, i32 %y, i32 %z.0, i32 %z.1, i32 %z.2) nounwind ssp {
; X86-LABEL: t11:
; X86: # %bb.0: # %entry
; X86-NEXT: cmpl $0, {{[0-9]+}}(%esp)
@@ -303,7 +303,7 @@ declare dso_local i32 @foo5(i32, i32, i32, i32, i32)
%struct.t = type { i32, i32, i32, i32, i32 }
-define i32 @t12(i32 %x, i32 %y, %struct.t* byval(%struct.t) align 4 %z) nounwind ssp {
+define dso_local i32 @t12(i32 %x, i32 %y, %struct.t* byval(%struct.t) align 4 %z) nounwind ssp {
; X86-LABEL: t12:
; X86: # %bb.0: # %entry
; X86-NEXT: cmpl $0, {{[0-9]+}}(%esp)
@@ -413,7 +413,7 @@ declare dso_local fastcc %struct.ns* @foo7(%struct.cp* byval(%struct.cp) align 4
%struct.__block_literal_1 = type { i8*, i32, i32, i8*, %struct.__block_descriptor* }
%struct.__block_literal_2 = type { i8*, i32, i32, i8*, %struct.__block_descriptor_withcopydispose*, void ()* }
-define void @t14(%struct.__block_literal_2* nocapture %.block_descriptor) nounwind ssp {
+define dso_local void @t14(%struct.__block_literal_2* nocapture %.block_descriptor) nounwind ssp {
; X86-LABEL: t14:
; X86: # %bb.0: # %entry
; X86-NEXT: subl $12, %esp
@@ -449,7 +449,7 @@ entry:
; rdar://7726868
%struct.foo = type { [4 x i32] }
-define void @t15(%struct.foo* noalias sret(%struct.foo) %agg.result) nounwind {
+define dso_local void @t15(%struct.foo* noalias sret(%struct.foo) %agg.result) nounwind {
; X86-LABEL: t15:
; X86: # %bb.0:
; X86-NEXT: pushl %esi
@@ -485,7 +485,7 @@ define void @t15(%struct.foo* noalias sret(%struct.foo) %agg.result) nounwind {
declare dso_local void @f(%struct.foo* noalias sret(%struct.foo)) nounwind
-define void @t16() nounwind ssp {
+define dso_local void @t16() nounwind ssp {
; X86-LABEL: t16:
; X86: # %bb.0: # %entry
; X86-NEXT: subl $12, %esp
@@ -509,7 +509,7 @@ entry:
declare dso_local double @bar4()
; rdar://6283267
-define void @t17() nounwind ssp {
+define dso_local void @t17() nounwind ssp {
; X86-LABEL: t17:
; X86: # %bb.0: # %entry
; X86-NEXT: jmp bar5 # TAILCALL
@@ -531,7 +531,7 @@ entry:
declare dso_local void @bar5(...)
; rdar://7774847
-define void @t18() nounwind ssp {
+define dso_local void @t18() nounwind ssp {
; X86-LABEL: t18:
; X86: # %bb.0: # %entry
; X86-NEXT: subl $12, %esp
@@ -556,7 +556,7 @@ entry:
declare dso_local double @bar6(...)
-define void @t19() alignstack(32) nounwind {
+define dso_local void @t19() alignstack(32) nounwind {
; X86-LABEL: t19:
; X86: # %bb.0: # %entry
; X86-NEXT: pushl %ebp
@@ -598,7 +598,7 @@ entry:
; values are returned in the same registers.
; rdar://7874780
-define double @t20(double %x) nounwind {
+define dso_local double @t20(double %x) nounwind {
; X86-LABEL: t20:
; X86: # %bb.0: # %entry
; X86-NEXT: subl $12, %esp
diff --git a/llvm/test/CodeGen/X86/speculative-execution-side-effect-suppression.ll b/llvm/test/CodeGen/X86/speculative-execution-side-effect-suppression.ll
index fdd56382448a..c1dee72e6d07 100644
--- a/llvm/test/CodeGen/X86/speculative-execution-side-effect-suppression.ll
+++ b/llvm/test/CodeGen/X86/speculative-execution-side-effect-suppression.ll
@@ -4,7 +4,7 @@
; RUN: llc -mtriple=x86_64-unknown-linux-gnu -x86-seses-enable-without-lvi-cfi -x86-seses-omit-branch-lfences %s -o - | FileCheck %s --check-prefix=X86-OMIT-BR
; RUN: llc -mtriple=x86_64-unknown-linux-gnu -x86-seses-enable-without-lvi-cfi -x86-seses-only-lfence-non-const %s -o - | FileCheck %s --check-prefix=X86-NON-CONST
-define void @_Z4buzzv() {
+define dso_local void @_Z4buzzv() {
; CHECK-LABEL: _Z4buzzv:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lfence
@@ -34,7 +34,7 @@ entry:
ret void
}
-define i32 @_Z3barPi(i32* %p) {
+define dso_local i32 @_Z3barPi(i32* %p) {
; CHECK-LABEL: _Z3barPi:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lfence
@@ -173,7 +173,7 @@ return: ; preds = %if.else, %if.then
ret i32 %7
}
-define i32 (i32*)* @_Z3bazv() {
+define dso_local i32 (i32*)* @_Z3bazv() {
; CHECK-LABEL: _Z3bazv:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lfence
@@ -223,7 +223,7 @@ entry:
ret i32 (i32*)* %0
}
-define void @_Z3fooPi(i32* %p) {
+define dso_local void @_Z3fooPi(i32* %p) {
; CHECK-LABEL: _Z3fooPi:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: subq $24, %rsp
diff --git a/llvm/test/CodeGen/X86/speculative-load-hardening-indirect.ll b/llvm/test/CodeGen/X86/speculative-load-hardening-indirect.ll
index e475c183c488..cb3ce4e52538 100644
--- a/llvm/test/CodeGen/X86/speculative-load-hardening-indirect.ll
+++ b/llvm/test/CodeGen/X86/speculative-load-hardening-indirect.ll
@@ -13,14 +13,14 @@
@global_fnptr = external global i32 ()*
- at global_blockaddrs = constant [4 x i8*] [
+ at global_blockaddrs = dso_local constant [4 x i8*] [
i8* blockaddress(@test_indirectbr_global, %bb0),
i8* blockaddress(@test_indirectbr_global, %bb1),
i8* blockaddress(@test_indirectbr_global, %bb2),
i8* blockaddress(@test_indirectbr_global, %bb3)
]
-define i32 @test_indirect_call(i32 ()** %ptr) nounwind {
+define dso_local i32 @test_indirect_call(i32 ()** %ptr) nounwind {
; X64-LABEL: test_indirect_call:
; X64: # %bb.0: # %entry
; X64-NEXT: pushq %rbx
@@ -93,7 +93,7 @@ entry:
ret i32 %v
}
-define i32 @test_indirect_tail_call(i32 ()** %ptr) nounwind {
+define dso_local i32 @test_indirect_tail_call(i32 ()** %ptr) nounwind {
; X64-LABEL: test_indirect_tail_call:
; X64: # %bb.0: # %entry
; X64-NEXT: movq %rsp, %rax
@@ -132,7 +132,7 @@ entry:
ret i32 %v
}
-define i32 @test_indirect_call_global() nounwind {
+define dso_local i32 @test_indirect_call_global() nounwind {
; X64-LABEL: test_indirect_call_global:
; X64: # %bb.0: # %entry
; X64-NEXT: pushq %rbx
@@ -208,7 +208,7 @@ entry:
ret i32 %v
}
-define i32 @test_indirect_tail_call_global() nounwind {
+define dso_local i32 @test_indirect_tail_call_global() nounwind {
; X64-LABEL: test_indirect_tail_call_global:
; X64: # %bb.0: # %entry
; X64-NEXT: movq %rsp, %rax
@@ -250,7 +250,7 @@ entry:
ret i32 %v
}
-define i32 @test_indirectbr(i8** %ptr) nounwind {
+define dso_local i32 @test_indirectbr(i8** %ptr) nounwind {
; X64-LABEL: test_indirectbr:
; X64: # %bb.0: # %entry
; X64-NEXT: movq %rsp, %rcx
@@ -356,7 +356,7 @@ bb3:
ret i32 42
}
-define i32 @test_indirectbr_global(i32 %idx) nounwind {
+define dso_local i32 @test_indirectbr_global(i32 %idx) nounwind {
; X64-LABEL: test_indirectbr_global:
; X64: # %bb.0: # %entry
; X64-NEXT: movq %rsp, %rcx
@@ -405,7 +405,7 @@ define i32 @test_indirectbr_global(i32 %idx) nounwind {
; X64-PIC-NEXT: movq $-1, %rax
; X64-PIC-NEXT: sarq $63, %rcx
; X64-PIC-NEXT: movslq %edi, %rdx
-; X64-PIC-NEXT: movq global_blockaddrs@{{.*}}(%rip), %rsi
+; X64-PIC-NEXT: leaq .Lglobal_blockaddrs$local(%rip), %rsi
; X64-PIC-NEXT: movq (%rsi,%rdx,8), %rdx
; X64-PIC-NEXT: orq %rcx, %rdx
; X64-PIC-NEXT: jmpq *%rdx
@@ -512,7 +512,7 @@ bb3:
; This function's switch is crafted to trigger jump-table lowering in the x86
; backend so that we can test how the exact jump table lowering behaves.
-define i32 @test_switch_jumptable(i32 %idx) nounwind {
+define dso_local i32 @test_switch_jumptable(i32 %idx) nounwind {
; X64-LABEL: test_switch_jumptable:
; X64: # %bb.0: # %entry
; X64-NEXT: movq %rsp, %rcx
@@ -704,7 +704,7 @@ bb5:
; backend so that we can test how the exact jump table lowering behaves, but
; also arranges for fallthroughs from case to case to ensure that this pattern
; too can be handled.
-define i32 @test_switch_jumptable_fallthrough(i32 %idx, i32* %a.ptr, i32* %b.ptr, i32* %c.ptr, i32* %d.ptr) nounwind {
+define dso_local i32 @test_switch_jumptable_fallthrough(i32 %idx, i32* %a.ptr, i32* %b.ptr, i32* %c.ptr, i32* %d.ptr) nounwind {
; X64-LABEL: test_switch_jumptable_fallthrough:
; X64: # %bb.0: # %entry
; X64-NEXT: movq %rsp, %r9
diff --git a/llvm/test/CodeGen/X86/splat-for-size.ll b/llvm/test/CodeGen/X86/splat-for-size.ll
index da68f069b078..55e1470226ed 100644
--- a/llvm/test/CodeGen/X86/splat-for-size.ll
+++ b/llvm/test/CodeGen/X86/splat-for-size.ll
@@ -382,7 +382,7 @@ define <32 x i8> @splat_v32i8_pgso(<32 x i8> %x) !prof !14 {
; due to a missing AVX pattern to select a v2i64 X86ISD::BROADCAST of a
; loadi64 with multiple uses.
- at A = common global <3 x i64> zeroinitializer, align 32
+ at A = common dso_local global <3 x i64> zeroinitializer, align 32
define <8 x i64> @pr23259() #1 {
; AVX-LABEL: pr23259:
diff --git a/llvm/test/CodeGen/X86/stores-merging.ll b/llvm/test/CodeGen/X86/stores-merging.ll
index 14dd43ed71a4..d92342ab7fa8 100644
--- a/llvm/test/CodeGen/X86/stores-merging.ll
+++ b/llvm/test/CodeGen/X86/stores-merging.ll
@@ -3,14 +3,14 @@
%structTy = type { i8, i32, i32 }
- at e = common global %structTy zeroinitializer, align 4
+ at e = common dso_local global %structTy zeroinitializer, align 4
;; Ensure that MergeConsecutiveStores doesn't incorrectly reorder
;; store operations. The first test stores in increasing address
;; order, the second in decreasing -- but in both cases should have
;; the same result in memory in the end.
-define void @redundant_stores_merging() {
+define dso_local void @redundant_stores_merging() {
; CHECK-LABEL: redundant_stores_merging:
; CHECK: # %bb.0:
; CHECK-NEXT: movabsq $1958505086977, %rax # imm = 0x1C800000001
@@ -23,7 +23,7 @@ define void @redundant_stores_merging() {
}
;; This variant tests PR25154.
-define void @redundant_stores_merging_reverse() {
+define dso_local void @redundant_stores_merging_reverse() {
; CHECK-LABEL: redundant_stores_merging_reverse:
; CHECK: # %bb.0:
; CHECK-NEXT: movabsq $528280977409, %rax # imm = 0x7B00000001
@@ -36,14 +36,14 @@ define void @redundant_stores_merging_reverse() {
ret void
}
- at b = common global [8 x i8] zeroinitializer, align 2
+ at b = common dso_local global [8 x i8] zeroinitializer, align 2
;; The 2-byte store to offset 3 overlaps the 2-byte store to offset 2;
;; these must not be reordered in MergeConsecutiveStores such that the
;; store to 3 comes first (e.g. by merging the stores to 0 and 2 into
;; a movl, after the store to 3).
-define void @overlapping_stores_merging() {
+define dso_local void @overlapping_stores_merging() {
; CHECK-LABEL: overlapping_stores_merging:
; CHECK: # %bb.0:
; CHECK-NEXT: movl $1, {{.*}}(%rip)
@@ -55,7 +55,7 @@ define void @overlapping_stores_merging() {
ret void
}
-define void @extract_vector_store_16_consecutive_bytes(<2 x i64> %v, i8* %ptr) #0 {
+define dso_local void @extract_vector_store_16_consecutive_bytes(<2 x i64> %v, i8* %ptr) #0 {
; CHECK-LABEL: extract_vector_store_16_consecutive_bytes:
; CHECK: # %bb.0:
; CHECK-NEXT: vmovups %xmm0, (%rdi)
@@ -114,7 +114,7 @@ define void @extract_vector_store_16_consecutive_bytes(<2 x i64> %v, i8* %ptr) #
; PR34217 - https://bugs.llvm.org/show_bug.cgi?id=34217
-define void @extract_vector_store_32_consecutive_bytes(<4 x i64> %v, i8* %ptr) #0 {
+define dso_local void @extract_vector_store_32_consecutive_bytes(<4 x i64> %v, i8* %ptr) #0 {
; CHECK-LABEL: extract_vector_store_32_consecutive_bytes:
; CHECK: # %bb.0:
; CHECK-NEXT: vmovups %ymm0, (%rdi)
@@ -221,7 +221,7 @@ define void @extract_vector_store_32_consecutive_bytes(<4 x i64> %v, i8* %ptr) #
}
; https://bugs.llvm.org/show_bug.cgi?id=43446
-define void @pr43446_0(i64 %x) {
+define dso_local void @pr43446_0(i64 %x) {
; CHECK-LABEL: pr43446_0:
; CHECK: # %bb.0:
; CHECK-NEXT: movb $1, (%rdi)
@@ -232,7 +232,7 @@ define void @pr43446_0(i64 %x) {
store i1 true, i1* %b, align 1
ret void
}
-define void @pr43446_1(i8* %a) {
+define dso_local void @pr43446_1(i8* %a) {
; CHECK-LABEL: pr43446_1:
; CHECK: # %bb.0:
; CHECK-NEXT: movb $1, (%rdi)
@@ -243,7 +243,7 @@ define void @pr43446_1(i8* %a) {
ret void
}
-define void @rotate16_in_place(i8* %p) {
+define dso_local void @rotate16_in_place(i8* %p) {
; CHECK-LABEL: rotate16_in_place:
; CHECK: # %bb.0:
; CHECK-NEXT: rolw $8, (%rdi)
@@ -257,7 +257,7 @@ define void @rotate16_in_place(i8* %p) {
ret void
}
-define void @rotate16(i8* %p, i8* %q) {
+define dso_local void @rotate16(i8* %p, i8* %q) {
; CHECK-LABEL: rotate16:
; CHECK: # %bb.0:
; CHECK-NEXT: movzwl (%rdi), %eax
@@ -275,7 +275,7 @@ define void @rotate16(i8* %p, i8* %q) {
ret void
}
-define void @rotate32_in_place(i16* %p) {
+define dso_local void @rotate32_in_place(i16* %p) {
; CHECK-LABEL: rotate32_in_place:
; CHECK: # %bb.0:
; CHECK-NEXT: roll $16, (%rdi)
@@ -289,7 +289,7 @@ define void @rotate32_in_place(i16* %p) {
ret void
}
-define void @rotate32(i16* %p) {
+define dso_local void @rotate32(i16* %p) {
; CHECK-LABEL: rotate32:
; CHECK: # %bb.0:
; CHECK-NEXT: movl (%rdi), %eax
@@ -307,7 +307,7 @@ define void @rotate32(i16* %p) {
ret void
}
-define void @rotate64_in_place(i32* %p) {
+define dso_local void @rotate64_in_place(i32* %p) {
; CHECK-LABEL: rotate64_in_place:
; CHECK: # %bb.0:
; CHECK-NEXT: rolq $32, (%rdi)
@@ -321,7 +321,7 @@ define void @rotate64_in_place(i32* %p) {
ret void
}
-define void @rotate64(i32* %p) {
+define dso_local void @rotate64(i32* %p) {
; CHECK-LABEL: rotate64:
; CHECK: # %bb.0:
; CHECK-NEXT: movq (%rdi), %rax
@@ -339,7 +339,7 @@ define void @rotate64(i32* %p) {
ret void
}
-define void @rotate64_iterate(i16* %p) {
+define dso_local void @rotate64_iterate(i16* %p) {
; CHECK-LABEL: rotate64_iterate:
; CHECK: # %bb.0:
; CHECK-NEXT: movq (%rdi), %rax
@@ -367,7 +367,7 @@ define void @rotate64_iterate(i16* %p) {
; TODO: recognize this as 2 rotates?
-define void @rotate32_consecutive(i16* %p) {
+define dso_local void @rotate32_consecutive(i16* %p) {
; CHECK-LABEL: rotate32_consecutive:
; CHECK: # %bb.0:
; CHECK-NEXT: movzwl (%rdi), %eax
@@ -400,7 +400,7 @@ define void @rotate32_consecutive(i16* %p) {
; Same as above, but now the stores are not all consecutive.
-define void @rotate32_twice(i16* %p) {
+define dso_local void @rotate32_twice(i16* %p) {
; CHECK-LABEL: rotate32_twice:
; CHECK: # %bb.0:
; CHECK-NEXT: movl (%rdi), %eax
@@ -429,7 +429,7 @@ define void @rotate32_twice(i16* %p) {
ret void
}
-define void @trunc_i16_to_i8(i16 %x, i8* %p) {
+define dso_local void @trunc_i16_to_i8(i16 %x, i8* %p) {
; CHECK-LABEL: trunc_i16_to_i8:
; CHECK: # %bb.0:
; CHECK-NEXT: movw %di, (%rsi)
@@ -443,7 +443,7 @@ define void @trunc_i16_to_i8(i16 %x, i8* %p) {
ret void
}
-define void @trunc_i32_to_i8(i32 %x, i8* %p) {
+define dso_local void @trunc_i32_to_i8(i32 %x, i8* %p) {
; CHECK-LABEL: trunc_i32_to_i8:
; CHECK: # %bb.0:
; CHECK-NEXT: movl %edi, (%rsi)
@@ -465,7 +465,7 @@ define void @trunc_i32_to_i8(i32 %x, i8* %p) {
ret void
}
-define void @trunc_i32_to_i16(i32 %x, i16* %p) {
+define dso_local void @trunc_i32_to_i16(i32 %x, i16* %p) {
; CHECK-LABEL: trunc_i32_to_i16:
; CHECK: # %bb.0:
; CHECK-NEXT: movl %edi, (%rsi)
@@ -479,7 +479,7 @@ define void @trunc_i32_to_i16(i32 %x, i16* %p) {
ret void
}
-define void @be_i32_to_i16(i32 %x, i16* %p0) {
+define dso_local void @be_i32_to_i16(i32 %x, i16* %p0) {
; CHECK-LABEL: be_i32_to_i16:
; CHECK: # %bb.0:
; CHECK-NEXT: rorl $16, %edi
@@ -494,7 +494,7 @@ define void @be_i32_to_i16(i32 %x, i16* %p0) {
ret void
}
-define void @be_i32_to_i16_order(i32 %x, i16* %p0) {
+define dso_local void @be_i32_to_i16_order(i32 %x, i16* %p0) {
; CHECK-LABEL: be_i32_to_i16_order:
; CHECK: # %bb.0:
; CHECK-NEXT: rorl $16, %edi
@@ -509,7 +509,7 @@ define void @be_i32_to_i16_order(i32 %x, i16* %p0) {
ret void
}
-define void @trunc_i64_to_i8(i64 %x, i8* %p) {
+define dso_local void @trunc_i64_to_i8(i64 %x, i8* %p) {
; CHECK-LABEL: trunc_i64_to_i8:
; CHECK: # %bb.0:
; CHECK-NEXT: movq %rdi, (%rsi)
@@ -547,7 +547,7 @@ define void @trunc_i64_to_i8(i64 %x, i8* %p) {
ret void
}
-define void @trunc_i64_to_i16(i64 %x, i16* %p) {
+define dso_local void @trunc_i64_to_i16(i64 %x, i16* %p) {
; CHECK-LABEL: trunc_i64_to_i16:
; CHECK: # %bb.0:
; CHECK-NEXT: movq %rdi, (%rsi)
@@ -569,7 +569,7 @@ define void @trunc_i64_to_i16(i64 %x, i16* %p) {
ret void
}
-define void @trunc_i64_to_i32(i64 %x, i32* %p) {
+define dso_local void @trunc_i64_to_i32(i64 %x, i32* %p) {
; CHECK-LABEL: trunc_i64_to_i32:
; CHECK: # %bb.0:
; CHECK-NEXT: movq %rdi, (%rsi)
@@ -583,7 +583,7 @@ define void @trunc_i64_to_i32(i64 %x, i32* %p) {
ret void
}
-define void @be_i64_to_i32(i64 %x, i32* %p0) {
+define dso_local void @be_i64_to_i32(i64 %x, i32* %p0) {
; CHECK-LABEL: be_i64_to_i32:
; CHECK: # %bb.0:
; CHECK-NEXT: rorq $32, %rdi
@@ -598,7 +598,7 @@ define void @be_i64_to_i32(i64 %x, i32* %p0) {
ret void
}
-define void @be_i64_to_i32_order(i64 %x, i32* %p0) {
+define dso_local void @be_i64_to_i32_order(i64 %x, i32* %p0) {
; CHECK-LABEL: be_i64_to_i32_order:
; CHECK: # %bb.0:
; CHECK-NEXT: rorq $32, %rdi
diff --git a/llvm/test/CodeGen/X86/subvector-broadcast.ll b/llvm/test/CodeGen/X86/subvector-broadcast.ll
index e2f5f366e96b..f031e7dcb08d 100644
--- a/llvm/test/CodeGen/X86/subvector-broadcast.ll
+++ b/llvm/test/CodeGen/X86/subvector-broadcast.ll
@@ -797,10 +797,10 @@ define <16 x i32> @test_broadcast_4i32_16i32_chain(<4 x i32>* %p0, <4 x float>*
; Fallback to the broadcast should be done
;
- at ga4 = global <4 x i64> zeroinitializer, align 8
- at gb4 = global <8 x i64> zeroinitializer, align 8
+ at ga4 = dso_local global <4 x i64> zeroinitializer, align 8
+ at gb4 = dso_local global <8 x i64> zeroinitializer, align 8
-define void @fallback_broadcast_v4i64_to_v8i64(<4 x i64> %a, <8 x i64> %b) {
+define dso_local void @fallback_broadcast_v4i64_to_v8i64(<4 x i64> %a, <8 x i64> %b) {
; X86-AVX1-LABEL: fallback_broadcast_v4i64_to_v8i64:
; X86-AVX1: # %bb.0: # %entry
; X86-AVX1-NEXT: vmovdqa {{.*#+}} xmm3 = [1,0,2,0]
@@ -912,10 +912,10 @@ entry:
}
- at ga2 = global <4 x double> zeroinitializer, align 8
- at gb2 = global <8 x double> zeroinitializer, align 8
+ at ga2 = dso_local global <4 x double> zeroinitializer, align 8
+ at gb2 = dso_local global <8 x double> zeroinitializer, align 8
-define void @fallback_broadcast_v4f64_to_v8f64(<4 x double> %a, <8 x double> %b) {
+define dso_local void @fallback_broadcast_v4f64_to_v8f64(<4 x double> %a, <8 x double> %b) {
; X86-AVX-LABEL: fallback_broadcast_v4f64_to_v8f64:
; X86-AVX: # %bb.0: # %entry
; X86-AVX-NEXT: vmovapd {{.*#+}} ymm3 = [1.0E+0,2.0E+0,3.0E+0,4.0E+0]
@@ -976,11 +976,11 @@ entry:
ret void
}
- at ha4 = global <4 x i32> zeroinitializer, align 8
- at hb4 = global <8 x i32> zeroinitializer, align 8
- at hc4 = global <16 x i32> zeroinitializer, align 8
+ at ha4 = dso_local global <4 x i32> zeroinitializer, align 8
+ at hb4 = dso_local global <8 x i32> zeroinitializer, align 8
+ at hc4 = dso_local global <16 x i32> zeroinitializer, align 8
-define void @fallback_broadcast_v4i32_v8i32_v16i32(<4 x i32> %a, <8 x i32> %b, <16 x i32> %c) nounwind {
+define dso_local void @fallback_broadcast_v4i32_v8i32_v16i32(<4 x i32> %a, <8 x i32> %b, <16 x i32> %c) nounwind {
; X86-AVX1-LABEL: fallback_broadcast_v4i32_v8i32_v16i32:
; X86-AVX1: # %bb.0: # %entry
; X86-AVX1-NEXT: pushl %ebp
diff --git a/llvm/test/CodeGen/X86/swift-return.ll b/llvm/test/CodeGen/X86/swift-return.ll
index fc3115405963..b2d1130a9b64 100644
--- a/llvm/test/CodeGen/X86/swift-return.ll
+++ b/llvm/test/CodeGen/X86/swift-return.ll
@@ -2,7 +2,7 @@
; RUN: llc -verify-machineinstrs < %s -mtriple=x86_64-unknown-unknown | FileCheck %s
; RUN: llc -verify-machineinstrs < %s -mtriple=x86_64-unknown-unknown -O0 | FileCheck --check-prefix=CHECK-O0 %s
- at var = global i32 0
+ at var = dso_local global i32 0
; Test how llvm handles return type of {i16, i8}. The return value will be
; passed in %eax and %dl.
@@ -54,7 +54,7 @@ declare swiftcc { i16, i8 } @gen(i32)
; If we can't pass every return value in register, we will pass everything
; in memroy. The caller provides space for the return value and passes
; the address in %rax. The first input argument will be in %rdi.
-define i32 @test2(i32 %key) #0 {
+define dso_local i32 @test2(i32 %key) #0 {
; CHECK-LABEL: test2:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: subq $24, %rsp
@@ -140,7 +140,7 @@ define swiftcc { i32, i32, i32, i32, i32 } @gen2(i32 %key) {
; The return value {i32, i32, i32, i32} will be returned via registers %eax,
; %edx, %ecx, %r8d.
-define i32 @test3(i32 %key) #0 {
+define dso_local i32 @test3(i32 %key) #0 {
; CHECK-LABEL: test3:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: pushq %rax
@@ -188,7 +188,7 @@ declare swiftcc { i32, i32, i32, i32 } @gen3(i32 %key)
; The return value {float, float, float, float} will be returned via registers
; %xmm0, %xmm1, %xmm2, %xmm3.
-define float @test4(float %key) #0 {
+define dso_local float @test4(float %key) #0 {
; CHECK-LABEL: test4:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: pushq %rax
@@ -234,7 +234,7 @@ entry:
declare swiftcc { float, float, float, float } @gen4(float %key)
-define void @consume_i1_ret() {
+define dso_local void @consume_i1_ret() {
; CHECK-LABEL: consume_i1_ret:
; CHECK: # %bb.0:
; CHECK-NEXT: pushq %rax
diff --git a/llvm/test/CodeGen/X86/tail-opts.ll b/llvm/test/CodeGen/X86/tail-opts.ll
index 06fa22a6c395..dc98c362b0d9 100644
--- a/llvm/test/CodeGen/X86/tail-opts.ll
+++ b/llvm/test/CodeGen/X86/tail-opts.ll
@@ -8,13 +8,13 @@ declare dso_local void @ear(i32)
declare dso_local void @far(i32)
declare i1 @qux()
- at GHJK = global i32 0
- at HABC = global i32 0
+ at GHJK = dso_local global i32 0
+ at HABC = dso_local global i32 0
; BranchFolding should tail-merge the stores since they all precede
; direct branches to the same place.
-define void @tail_merge_me() nounwind {
+define dso_local void @tail_merge_me() nounwind {
; CHECK-LABEL: tail_merge_me:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: pushq %rax
@@ -92,7 +92,7 @@ declare i8* @choose(i8*, i8*)
; BranchFolding should tail-duplicate the indirect jump to avoid
; redundant branching.
-define void @tail_duplicate_me() nounwind {
+define dso_local void @tail_duplicate_me() nounwind {
; CHECK-LABEL: tail_duplicate_me:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: pushq %r14
@@ -401,7 +401,7 @@ declare fastcc %union.tree_node* @default_conversion(%union.tree_node*) nounwind
; instructions are involved. This function should have only
; one ret instruction.
-define void @foo(i1* %V) nounwind {
+define dso_local void @foo(i1* %V) nounwind {
; CHECK-LABEL: foo:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: testq %rdi, %rdi
@@ -432,7 +432,7 @@ declare dso_local void @func()
declare dso_local void @tail_call_me()
-define void @one(i32 %v) nounwind optsize {
+define dso_local void @one(i32 %v) nounwind optsize {
; CHECK-LABEL: one:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: testl %edi, %edi
@@ -473,7 +473,7 @@ return:
ret void
}
-define void @one_pgso(i32 %v) nounwind !prof !14 {
+define dso_local void @one_pgso(i32 %v) nounwind !prof !14 {
; CHECK-LABEL: one_pgso:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: testl %edi, %edi
@@ -518,7 +518,7 @@ return:
; tail instead of one. This is too much to be merged, given
; the optsize attribute.
-define void @two() nounwind optsize {
+define dso_local void @two() nounwind optsize {
; CHECK-LABEL: two:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xorl %eax, %eax
@@ -559,7 +559,7 @@ return:
ret void
}
-define void @two_pgso() nounwind !prof !14 {
+define dso_local void @two_pgso() nounwind !prof !14 {
; CHECK-LABEL: two_pgso:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xorl %eax, %eax
@@ -602,7 +602,7 @@ return:
; two_minsize - Same as two, but with minsize instead of optsize.
-define void @two_minsize() nounwind minsize {
+define dso_local void @two_minsize() nounwind minsize {
; CHECK-LABEL: two_minsize:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xorl %eax, %eax
@@ -646,7 +646,7 @@ return:
; two_nosize - Same as two, but without the optsize attribute.
; Now two instructions are enough to be tail-duplicated.
-define void @two_nosize(i32 %x, i32 %y, i32 %z) nounwind {
+define dso_local void @two_nosize(i32 %x, i32 %y, i32 %z) nounwind {
; CHECK-LABEL: two_nosize:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: testl %edi, %edi
@@ -729,7 +729,7 @@ for.end: ; preds = %entry
; them as possible.
declare dso_local void @abort()
-define void @merge_aborts() {
+define dso_local void @merge_aborts() {
; CHECK-LABEL: merge_aborts:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: pushq %rax
@@ -789,7 +789,7 @@ cont4:
declare dso_local void @alt_abort()
-define void @merge_alternating_aborts() {
+define dso_local void @merge_alternating_aborts() {
; CHECK-LABEL: merge_alternating_aborts:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: pushq %rax
@@ -848,8 +848,8 @@ cont4:
; This triggers a situation where a new block (bb4 is split) is created and then
; would be passed to the PGSO interface llvm::shouldOptimizeForSize().
- at GV = global i32 0
-define void @bfi_new_block_pgso(i32 %c) nounwind {
+ at GV = dso_local global i32 0
+define dso_local void @bfi_new_block_pgso(i32 %c) nounwind {
; CHECK-LABEL: bfi_new_block_pgso:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: testl %edi, %edi
diff --git a/llvm/test/CodeGen/X86/tailcall-disable.ll b/llvm/test/CodeGen/X86/tailcall-disable.ll
index 1fd2d72dc570..165234b0898a 100644
--- a/llvm/test/CodeGen/X86/tailcall-disable.ll
+++ b/llvm/test/CodeGen/X86/tailcall-disable.ll
@@ -4,12 +4,12 @@
target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"
-define i32 @helper() nounwind {
+define dso_local i32 @helper() nounwind {
entry:
ret i32 7
}
-define i32 @test1() nounwind {
+define dso_local i32 @test1() nounwind {
entry:
%call = tail call i32 @helper()
ret i32 %call
@@ -24,7 +24,7 @@ entry:
; JMP-NOT: ret
; JMP: jmp helper # TAILCALL
-define i32 @test2() nounwind {
+define dso_local i32 @test2() nounwind {
entry:
%call = tail call i32 @test2()
ret i32 %call
diff --git a/llvm/test/CodeGen/X86/tailcall-tailcc.ll b/llvm/test/CodeGen/X86/tailcall-tailcc.ll
index 0b9e599d13fb..dda648741358 100644
--- a/llvm/test/CodeGen/X86/tailcall-tailcc.ll
+++ b/llvm/test/CodeGen/X86/tailcall-tailcc.ll
@@ -7,7 +7,7 @@
declare dso_local tailcc i32 @tailcallee(i32 %a1, i32 %a2, i32 %a3, i32 %a4)
-define tailcc i32 @tailcaller(i32 %in1, i32 %in2) nounwind {
+define dso_local tailcc i32 @tailcaller(i32 %in1, i32 %in2) nounwind {
; X64-LABEL: tailcaller:
; X64: # %bb.0: # %entry
; X64-NEXT: pushq %rax
@@ -48,7 +48,7 @@ define tailcc noalias i8* @noalias_caller() nounwind {
declare dso_local tailcc noalias i8* @noalias_callee()
-define tailcc i8* @alias_caller() nounwind {
+define dso_local tailcc i8* @alias_caller() nounwind {
; X64-LABEL: alias_caller:
; X64: # %bb.0:
; X64-NEXT: pushq %rax
@@ -64,7 +64,7 @@ define tailcc i8* @alias_caller() nounwind {
declare dso_local tailcc i32 @i32_callee()
-define tailcc i32 @ret_undef() nounwind {
+define dso_local tailcc i32 @ret_undef() nounwind {
; X64-LABEL: ret_undef:
; X64: # %bb.0:
; X64-NEXT: pushq %rax
@@ -80,7 +80,7 @@ define tailcc i32 @ret_undef() nounwind {
declare dso_local tailcc void @does_not_return()
-define tailcc i32 @noret() nounwind {
+define dso_local tailcc i32 @noret() nounwind {
; X64-LABEL: noret:
; X64: # %bb.0:
; X64-NEXT: pushq %rax
@@ -94,7 +94,7 @@ define tailcc i32 @noret() nounwind {
unreachable
}
-define tailcc void @void_test(i32, i32, i32, i32) {
+define dso_local tailcc void @void_test(i32, i32, i32, i32) {
; X64-LABEL: void_test:
; X64: # %bb.0: # %entry
; X64-NEXT: pushq %rax
@@ -124,7 +124,7 @@ define tailcc void @void_test(i32, i32, i32, i32) {
ret void
}
-define tailcc i1 @i1test(i32, i32, i32, i32) {
+define dso_local tailcc i1 @i1test(i32, i32, i32, i32) {
; X64-LABEL: i1test:
; X64: # %bb.0: # %entry
; X64-NEXT: pushq %rax
diff --git a/llvm/test/CodeGen/X86/tailcall.ll b/llvm/test/CodeGen/X86/tailcall.ll
index b70c11e20c56..6026a89bcc32 100644
--- a/llvm/test/CodeGen/X86/tailcall.ll
+++ b/llvm/test/CodeGen/X86/tailcall.ll
@@ -6,7 +6,7 @@
declare fastcc i32 @tailcallee(i32 %a1, i32 %a2, i32 %a3, i32 %a4)
-define fastcc i32 @tailcaller(i32 %in1, i32 %in2) nounwind {
+define dso_local fastcc i32 @tailcaller(i32 %in1, i32 %in2) nounwind {
; CHECK-LABEL: tailcaller:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: subl $16, %esp
@@ -33,7 +33,7 @@ define fastcc noalias i8* @noalias_caller() nounwind {
declare fastcc noalias i8* @noalias_callee()
-define fastcc i8* @alias_caller() nounwind {
+define dso_local fastcc i8* @alias_caller() nounwind {
; CHECK-LABEL: alias_caller:
; CHECK: # %bb.0:
; CHECK-NEXT: jmp noalias_callee at PLT # TAILCALL
@@ -43,7 +43,7 @@ define fastcc i8* @alias_caller() nounwind {
declare fastcc i32 @i32_callee()
-define fastcc i32 @ret_undef() nounwind {
+define dso_local fastcc i32 @ret_undef() nounwind {
; CHECK-LABEL: ret_undef:
; CHECK: # %bb.0:
; CHECK-NEXT: jmp i32_callee at PLT # TAILCALL
@@ -53,7 +53,7 @@ define fastcc i32 @ret_undef() nounwind {
declare fastcc void @does_not_return()
-define fastcc i32 @noret() nounwind {
+define dso_local fastcc i32 @noret() nounwind {
; CHECK-LABEL: noret:
; CHECK: # %bb.0:
; CHECK-NEXT: jmp does_not_return at PLT # TAILCALL
@@ -61,7 +61,7 @@ define fastcc i32 @noret() nounwind {
unreachable
}
-define fastcc void @void_test(i32, i32, i32, i32) {
+define dso_local fastcc void @void_test(i32, i32, i32, i32) {
; CHECK-LABEL: void_test:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: pushl %esi
@@ -83,7 +83,7 @@ define fastcc void @void_test(i32, i32, i32, i32) {
ret void
}
-define fastcc i1 @i1test(i32, i32, i32, i32) {
+define dso_local fastcc i1 @i1test(i32, i32, i32, i32) {
; CHECK-LABEL: i1test:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: pushl %esi
diff --git a/llvm/test/CodeGen/X86/test-shrink-bug.ll b/llvm/test/CodeGen/X86/test-shrink-bug.ll
index b9f67d132119..9a7d5f2b53ca 100644
--- a/llvm/test/CodeGen/X86/test-shrink-bug.ll
+++ b/llvm/test/CodeGen/X86/test-shrink-bug.ll
@@ -2,11 +2,11 @@
; RUN: llc < %s -mtriple=i386-apple-darwin10.0 | FileCheck %s --check-prefix=CHECK-X86
; RUN: llc < %s -mtriple=x86_64-grtev4-linux-gnu | FileCheck %s --check-prefix=CHECK-X64
- at g_14 = global i8 -6, align 1 ; <i8*> [#uses=1]
+ at g_14 = dso_local global i8 -6, align 1 ; <i8*> [#uses=1]
declare i32 @func_16(i8 signext %p_19, i32 %p_20) nounwind
-define i32 @func_35(i64 %p_38) nounwind ssp {
+define dso_local i32 @func_35(i64 %p_38) nounwind ssp {
; CHECK-X86-LABEL: func_35:
; CHECK-X86: ## %bb.0: ## %entry
; CHECK-X86-NEXT: subl $12, %esp
@@ -43,7 +43,7 @@ entry:
ret i32 1
}
-define void @fail(i16 %a, <2 x i8> %b) {
+define dso_local void @fail(i16 %a, <2 x i8> %b) {
; CHECK-X86-LABEL: fail:
; CHECK-X86: ## %bb.0:
; CHECK-X86-NEXT: subl $12, %esp
diff --git a/llvm/test/CodeGen/X86/tls-pie.ll b/llvm/test/CodeGen/X86/tls-pie.ll
index 854482a775d3..0659f287c1b2 100644
--- a/llvm/test/CodeGen/X86/tls-pie.ll
+++ b/llvm/test/CodeGen/X86/tls-pie.ll
@@ -3,10 +3,10 @@
; RUN: llc < %s -mcpu=generic -mtriple=x86_64-linux-gnux32 -relocation-model=pic | FileCheck %s --check-prefix=X32
; RUN: llc < %s -mcpu=generic -mtriple=x86_64-linux-gnu -relocation-model=pic | FileCheck %s --check-prefix=X64
- at i = thread_local global i32 15
+ at i = dso_local thread_local global i32 15
@i2 = external thread_local global i32
-define i32 @f1() {
+define dso_local i32 @f1() {
; X86-LABEL: f1:
; X86: # %bb.0: # %entry
; X86-NEXT: movl %gs:i at NTPOFF, %eax
@@ -26,7 +26,7 @@ entry:
ret i32 %tmp1
}
-define i32* @f2() {
+define dso_local i32* @f2() {
; X86-LABEL: f2:
; X86: # %bb.0: # %entry
; X86-NEXT: movl %gs:0, %eax
@@ -48,7 +48,7 @@ entry:
ret i32* @i
}
-define i32 @f3() {
+define dso_local i32 @f3() {
; X86-LABEL: f3:
; X86: # %bb.0: # %entry
; X86-NEXT: calll .L2$pb
@@ -79,7 +79,7 @@ entry:
ret i32 %tmp1
}
-define i32* @f4() {
+define dso_local i32* @f4() {
; X86-LABEL: f4:
; X86: # %bb.0: # %entry
; X86-NEXT: calll .L3$pb
diff --git a/llvm/test/CodeGen/X86/tls.ll b/llvm/test/CodeGen/X86/tls.ll
index 759f3d7c8550..ca52677fc8ad 100644
--- a/llvm/test/CodeGen/X86/tls.ll
+++ b/llvm/test/CodeGen/X86/tls.ll
@@ -7,17 +7,17 @@
; RUN: llc < %s -mtriple=i686-pc-windows-gnu | FileCheck -check-prefix=MINGW32 %s
; RUN: llc < %s -mtriple=x86_64-pc-windows-gnu | FileCheck -check-prefix=X64_WIN %s
- at i1 = thread_local global i32 15
+ at i1 = dso_local thread_local global i32 15
@i2 = external thread_local global i32
@i3 = internal thread_local global i32 15
@i4 = hidden thread_local global i32 15
@i5 = external hidden thread_local global i32
@i6 = external protected thread_local global i32
- at s1 = thread_local global i16 15
- at b1 = thread_local global i8 0
- at b2 = thread_local(localexec) global i8 0
+ at s1 = dso_local thread_local global i16 15
+ at b1 = dso_local thread_local global i8 0
+ at b2 = dso_local thread_local(localexec) global i8 0
-define i32 @f1() {
+define dso_local i32 @f1() {
; X86_LINUX-LABEL: f1:
; X86_LINUX: movl %gs:i1 at NTPOFF, %eax
; X86_LINUX-NEXT: ret
@@ -48,7 +48,7 @@ entry:
ret i32 %tmp1
}
-define i32* @f2() {
+define dso_local i32* @f2() {
; X86_LINUX-LABEL: f2:
; X86_LINUX: movl %gs:0, %eax
; X86_LINUX-NEXT: leal i1 at NTPOFF(%eax), %eax
@@ -80,7 +80,7 @@ entry:
ret i32* @i1
}
-define i32 @f3() nounwind {
+define dso_local i32 @f3() nounwind {
; X86_LINUX-LABEL: f3:
; X86_LINUX: movl i2 at INDNTPOFF, %eax
; X86_LINUX-NEXT: movl %gs:(%eax), %eax
@@ -113,7 +113,7 @@ entry:
ret i32 %tmp1
}
-define i32* @f4() {
+define dso_local i32* @f4() {
; X86_LINUX-LABEL: f4:
; X86_LINUX: movl %gs:0, %eax
; X86_LINUX-NEXT: addl i2 at INDNTPOFF, %eax
@@ -145,7 +145,7 @@ entry:
ret i32* @i2
}
-define i32 @f5() nounwind {
+define dso_local i32 @f5() nounwind {
; X86_LINUX-LABEL: f5:
; X86_LINUX: movl %gs:i3 at NTPOFF, %eax
; X86_LINUX-NEXT: ret
@@ -176,7 +176,7 @@ entry:
ret i32 %tmp1
}
-define i32* @f6() {
+define dso_local i32* @f6() {
; X86_LINUX-LABEL: f6:
; X86_LINUX: movl %gs:0, %eax
; X86_LINUX-NEXT: leal i3 at NTPOFF(%eax), %eax
@@ -208,7 +208,7 @@ entry:
ret i32* @i3
}
-define i32 @f7() {
+define dso_local i32 @f7() {
; X86_LINUX-LABEL: f7:
; X86_LINUX: movl %gs:i4 at NTPOFF, %eax
; X86_LINUX-NEXT: ret
@@ -227,7 +227,7 @@ entry:
ret i32 %tmp1
}
-define i32* @f8() {
+define dso_local i32* @f8() {
; X86_LINUX-LABEL: f8:
; X86_LINUX: movl %gs:0, %eax
; X86_LINUX-NEXT: leal i4 at NTPOFF(%eax), %eax
@@ -247,7 +247,7 @@ entry:
ret i32* @i4
}
-define i32 @f9() {
+define dso_local i32 @f9() {
; X86_LINUX-LABEL: f9:
; X86_LINUX: movl %gs:i5 at NTPOFF, %eax
; X86_LINUX-NEXT: ret
@@ -266,7 +266,7 @@ entry:
ret i32 %tmp1
}
-define i32* @f10() {
+define dso_local i32* @f10() {
; X86_LINUX-LABEL: f10:
; X86_LINUX: movl %gs:0, %eax
; X86_LINUX-NEXT: leal i5 at NTPOFF(%eax), %eax
@@ -317,7 +317,7 @@ entry:
ret i16 %tmp1
}
-define i32 @f12() {
+define dso_local i32 @f12() {
; X86_LINUX-LABEL: f12:
; X86_LINUX: movswl %gs:s1 at NTPOFF, %eax
; X86_LINUX-NEXT: ret
@@ -350,7 +350,7 @@ entry:
ret i32 %tmp2
}
-define i8 @f13() {
+define dso_local i8 @f13() {
; X86_LINUX-LABEL: f13:
; X86_LINUX: movb %gs:b1 at NTPOFF, %al
; X86_LINUX-NEXT: ret
@@ -381,7 +381,7 @@ entry:
ret i8 %tmp1
}
-define i32 @f14() {
+define dso_local i32 @f14() {
; X86_LINUX-LABEL: f14:
; X86_LINUX: movsbl %gs:b1 at NTPOFF, %eax
; X86_LINUX-NEXT: ret
@@ -413,7 +413,7 @@ entry:
ret i32 %tmp2
}
-define i8* @f15() {
+define dso_local i8* @f15() {
; X86_LINUX-LABEL: f15:
; X86_LINUX: movl %gs:0, %eax
; X86_LINUX-NEXT: leal b2 at NTPOFF(%eax), %eax
@@ -442,7 +442,7 @@ entry:
}
-define i32* @f16() {
+define dso_local i32* @f16() {
; X86_LINUX-LABEL: f16:
; X86_LINUX: movl %gs:0, %eax
; X86_LINUX-NEXT: leal i6 at NTPOFF(%eax), %eax
@@ -457,7 +457,7 @@ define i32* @f16() {
}
; NOTE: Similar to f1() but with direct TLS segment access disabled
-define i32 @f17() #0 {
+define dso_local i32 @f17() #0 {
; X86_LINUX-LABEL: f17:
; X86_LINUX: movl %gs:0, %eax
; X86_LINUX-NEXT: movl i1 at NTPOFF(%eax), %eax
@@ -481,7 +481,7 @@ entry:
}
; NOTE: Similar to f3() but with direct TLS segment access disabled
-define i32 @f18() #1 {
+define dso_local i32 @f18() #1 {
; X86_LINUX-LABEL: f18:
; X86_LINUX: movl i2 at INDNTPOFF, %eax
; X86_LINUX-NEXT: movl %gs:0, %ecx
diff --git a/llvm/test/CodeGen/X86/trunc-and.ll b/llvm/test/CodeGen/X86/trunc-and.ll
index 09fe6413d27a..812f838e36f0 100644
--- a/llvm/test/CodeGen/X86/trunc-and.ll
+++ b/llvm/test/CodeGen/X86/trunc-and.ll
@@ -28,9 +28,9 @@ declare <2 x double> @llvm.fabs.v2f64(<2 x double>)
%struct.anon = type { [9 x i8], [3 x i8] }
- at b = common local_unnamed_addr global %struct.anon zeroinitializer, align 4
+ at b = common dso_local local_unnamed_addr global %struct.anon zeroinitializer, align 4
-define i32 @d() {
+define dso_local i32 @d() {
; CHECK-LABEL: d:
; CHECK: # %bb.0:
; CHECK-NEXT: movzbl b+{{.*}}(%rip), %ecx
diff --git a/llvm/test/CodeGen/X86/undef-label.ll b/llvm/test/CodeGen/X86/undef-label.ll
index 56e0ca907f8e..2509667ae071 100644
--- a/llvm/test/CodeGen/X86/undef-label.ll
+++ b/llvm/test/CodeGen/X86/undef-label.ll
@@ -4,9 +4,9 @@
; This is a case where we would incorrectly conclude that LBB0_1 could only
; be reached via fall through and would therefore omit the label.
- at g = global i32 0
+ at g = dso_local global i32 0
-define void @xyz() {
+define dso_local void @xyz() {
; CHECK-LABEL: xyz:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: movl $g, %eax
diff --git a/llvm/test/CodeGen/X86/vec-loadsingles-alignment.ll b/llvm/test/CodeGen/X86/vec-loadsingles-alignment.ll
index ee3bfb311adf..aa00b63cadb8 100644
--- a/llvm/test/CodeGen/X86/vec-loadsingles-alignment.ll
+++ b/llvm/test/CodeGen/X86/vec-loadsingles-alignment.ll
@@ -1,12 +1,12 @@
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2 | FileCheck %s
- at e = global [8 x i32] [i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8], align 16
- at d = global [8 x i32] [i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1], align 16
+ at e = dso_local global [8 x i32] [i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8], align 16
+ at d = dso_local global [8 x i32] [i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1], align 16
; The global 'e' has 16 byte alignment, so make sure we don't generate an
; aligned 32-byte load instruction when we combine the load+insert sequence.
-define i32 @subb() nounwind ssp {
+define dso_local i32 @subb() nounwind ssp {
; CHECK-LABEL: subb:
; CHECK: vmovups e(%rip), %ymm
entry:
diff --git a/llvm/test/CodeGen/X86/widen_load-1.ll b/llvm/test/CodeGen/X86/widen_load-1.ll
index 8cbf8c4e3468..af8513ef5b43 100644
--- a/llvm/test/CodeGen/X86/widen_load-1.ll
+++ b/llvm/test/CodeGen/X86/widen_load-1.ll
@@ -13,11 +13,11 @@
; AVX: vmovaps %xmm0, (%rsp)
; AVX: callq killcommon
- at compl = linkonce global [20 x i64] zeroinitializer, align 64 ; <[20 x i64]*> [#uses=1]
+ at compl = linkonce dso_local global [20 x i64] zeroinitializer, align 64 ; <[20 x i64]*> [#uses=1]
declare void @killcommon(i32* noalias)
-define void @reset(<2 x float>* noalias %garbage1) {
+define dso_local void @reset(<2 x float>* noalias %garbage1) {
"file complex.c, line 27, bb1":
%changed = alloca i32, align 4 ; <i32*> [#uses=3]
br label %"file complex.c, line 27, bb13"
diff --git a/llvm/test/CodeGen/X86/x86-64-intrcc.ll b/llvm/test/CodeGen/X86/x86-64-intrcc.ll
index c371d67588a3..1b139b1fe503 100644
--- a/llvm/test/CodeGen/X86/x86-64-intrcc.ll
+++ b/llvm/test/CodeGen/X86/x86-64-intrcc.ll
@@ -3,8 +3,8 @@
%struct.interrupt_frame = type { i64, i64, i64, i64, i64 }
- at sink_address = global i64* null
- at sink_i32 = global i64 0
+ at sink_address = dso_local global i64* null
+ at sink_i32 = dso_local global i64 0
; Spills rax, putting original esp at +8.
; No stack adjustment if declared with no error code
@@ -90,7 +90,7 @@ define x86_intrcc void @test_isr_clobbers(%struct.interrupt_frame* byval(%struct
ret void
}
- at f80 = common global x86_fp80 0xK00000000000000000000, align 4
+ at f80 = common dso_local global x86_fp80 0xK00000000000000000000, align 4
; Test that the presence of x87 does not crash the FP stackifier
define x86_intrcc void @test_isr_x87(%struct.interrupt_frame* byval(%struct.interrupt_frame) %frame) {
diff --git a/llvm/test/CodeGen/X86/xor-select-i1-combine.ll b/llvm/test/CodeGen/X86/xor-select-i1-combine.ll
index 8ba7f7d931d4..65d7b3b35df5 100644
--- a/llvm/test/CodeGen/X86/xor-select-i1-combine.ll
+++ b/llvm/test/CodeGen/X86/xor-select-i1-combine.ll
@@ -1,10 +1,10 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
;RUN: llc < %s -O2 -mattr=+avx512f -mtriple=x86_64-unknown | FileCheck %s
- at n = common global i32 0, align 4
- at m = common global i32 0, align 4
+ at n = common dso_local global i32 0, align 4
+ at m = common dso_local global i32 0, align 4
-define i32 @main(i8 %small) {
+define dso_local i32 @main(i8 %small) {
; CHECK-LABEL: main:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: testb $1, %dil
@@ -22,7 +22,7 @@ entry:
}
-define i32 @main2(i8 %small) {
+define dso_local i32 @main2(i8 %small) {
; CHECK-LABEL: main2:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: movl $m, %eax
diff --git a/llvm/test/CodeGen/X86/xray-tail-call-sled.ll b/llvm/test/CodeGen/X86/xray-tail-call-sled.ll
index b3a7e24cc3e2..d109cf1c3dea 100644
--- a/llvm/test/CodeGen/X86/xray-tail-call-sled.ll
+++ b/llvm/test/CodeGen/X86/xray-tail-call-sled.ll
@@ -1,7 +1,7 @@
; RUN: llc -verify-machineinstrs -filetype=asm -o - -mtriple=x86_64-unknown-linux-gnu < %s | FileCheck %s
; RUN: llc -verify-machineinstrs -filetype=asm -o - -mtriple=x86_64-darwin-unknown < %s | FileCheck %s
-define i32 @callee() nounwind noinline uwtable "function-instrument"="xray-always" {
+define dso_local i32 @callee() nounwind noinline uwtable "function-instrument"="xray-always" {
; CHECK: .p2align 1, 0x90
; CHECK-LABEL: Lxray_sled_0:
; CHECK: .ascii "\353\t"
@@ -21,7 +21,7 @@ define i32 @callee() nounwind noinline uwtable "function-instrument"="xray-alway
; CHECK: .quad {{.*}}xray_sleds_start0
; CHECK-NEXT: .quad {{.*}}xray_sleds_end0
-define i32 @caller() nounwind noinline uwtable "function-instrument"="xray-always" {
+define dso_local i32 @caller() nounwind noinline uwtable "function-instrument"="xray-always" {
; CHECK: .p2align 1, 0x90
; CHECK-LABEL: Lxray_sled_2:
; CHECK: .ascii "\353\t"
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