[PATCH] D93867: [RISCV] Add earlyclobber of destination register to vmsbf.m/vmsif.m/vmsof.m instructions

[Craig Topper via Phabricator via llvm-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rG2ae760e27e6a: [RISCV] Add earlyclobber of destination register to vmsbf.m/vmsif.m/vmsof.m… (authored by craig.topper).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D93867/new/

https://reviews.llvm.org/D93867

Files:
  llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
  llvm/test/CodeGen/RISCV/rvv/vmsbf-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vmsbf-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vmsif-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vmsif-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vmsof-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vmsof-rv64.ll

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