[PATCH] D93898: [X86] Fix tile register spill issue.

[LuoYuanke via Phabricator via llvm-commits]

LuoYuanke created this revision.
Herald added subscribers: pengfei, hiraditya, qcolombet.
LuoYuanke requested review of this revision.
Herald added a project: LLVM.
Herald added a subscriber: llvm-commits.

The tile register spill need 2 instructions.
%46:gr64_nosp = MOV64ri 64
TILESTORED %stack.2, 1, killed %46:gr64_nosp, 0, $noreg, %43:tile
The first instruction load the stride to a GPR, and the second
instruction store tile register to stack slot. The optimization of merge
spill instruction is done after register allocation. And spill tile
register need create a new virtual register to for stride, so we can't
hoist tile spill instruction in postOptimization() of register
allocation. We can't hoist TILESTORED alone and we can't hoist the 2
instuctions together because MOV64ri will clobber some GPR. This patch
is to disble the spill merge for any spill which need 2 instructions.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D93898

Files:
  llvm/lib/CodeGen/InlineSpiller.cpp
  llvm/test/CodeGen/X86/AMX/amx-spill-merge.ll

-------------- next part --------------
A non-text attachment was scrubbed...
Name: D93898.313959.patch
Type: text/x-patch
Size: 10870 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20201229/42ea36ce/attachment.bin>