[PATCH] D93893: [RISCV] Define vsext/vzext intrinsics.

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


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Comment at: llvm/lib/Target/RISCV/RISCVRegisterInfo.td:456
+// Represent invalid LMUL register classes in LMULInfo.
+def NoVReg : VReg<[vint8m1_t], (add V0), 1>;
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Is this really needed? It was already introduced once and removed in a later patch. If it’s never going to be used can we just use an existing register class?


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  https://reviews.llvm.org/D93893/new/

https://reviews.llvm.org/D93893