[PATCH] D93894: [PowerPC] Expand BitPermutation to handle cases of the single immediate 'and'.

[EsmeYi via Phabricator via llvm-commits]

Esme created this revision.
Esme added reviewers: steven.zhang, shchenz, jsji, hfinkel, nemanjai, qiucf, lkail, PowerPC.
Herald added subscribers: kbarton, hiraditya.
Esme requested review of this revision.
Herald added a project: LLVM.
Herald added a subscriber: llvm-commits.

We have an overall procedure, the BitPermutation, to optimize ROTL, SHL, SRL, AND and OR. It builds up a list of collected and sorted bit groups and then ISel the entire permutation using a combination of masked rotations.

Currently BitPermutation excludes the input of a single immediate 'and', which will be transformed later through analyzing the patterns, ie. handled by the tryAs__() functions. However these patterns can only cover some specific cases, and for some other cases, BitPermutation can use fewer instructions for matching. Besides, I think it's reasonable to perform these transformations within BitPermutation since they have similar semantics with the BitPermutation.

This patch is trying to expand the BitPermutation to handle the case of single immediate 'and', therefore we can optimize more cases than the enumerated patterns.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D93894

Files:
  llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
  llvm/test/CodeGen/PowerPC/2016-04-17-combine.ll
  llvm/test/CodeGen/PowerPC/Frames-dyn-alloca.ll
  llvm/test/CodeGen/PowerPC/and-mask.ll
  llvm/test/CodeGen/PowerPC/andc.ll
  llvm/test/CodeGen/PowerPC/fp-to-int-to-fp.ll
  llvm/test/CodeGen/PowerPC/opt-cmp-inst-cr0-live.ll
  llvm/test/CodeGen/PowerPC/popcnt-zext.ll
  llvm/test/CodeGen/PowerPC/pr46759.ll
  llvm/test/CodeGen/PowerPC/pr47373.ll
  llvm/test/CodeGen/PowerPC/setcc-logic.ll
  llvm/test/CodeGen/PowerPC/stack-clash-dynamic-alloca.ll
  llvm/test/CodeGen/PowerPC/stack-clash-prologue.ll

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