[PATCH] D93878: [RISCV] Don't use tail agnostic policy on instructions where destination is tied to source

[Zakk Chen via Phabricator via llvm-commits]

khchen accepted this revision.
khchen added a comment.
This revision is now accepted and ready to land.

thanks for fixup, LGTM.



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Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:2151
+  bool TailAgnostic = true;
+  if (MI.isRegTiedToUseOperand(0) && !WritesElement0)
+    TailAgnostic = false;
----------------
craig.topper wrote:
> khchen wrote:
> > If the tail policy is ignored on WritesElement0 instructions, why not set tail policy as `tu`? 
> > Is it because spec said `If anything, the default should be tail-agnostic/mask-agnostic, so software has to specify when it cares about the non-participating elements`?
> > 
> > If we set anything as `tu` except undefined maskedoff, could it also make vsetvli removal easier.
> > 
> > 
> tu is bad for performance on a core implementing out of order or super scalar execution of vector instructions. It prevents an instruction from executing until the last instruction that wrote its destination register finishes executing even if they aren't related instructions. So I think it will be important for performance.
> 
> I left ta on the WriteElement0 instructions since that's what we use on vsetvli intrinsics so I was hoping to eliminate unnecessary vtype changes assuming ta is more common. But its admittedly a simple policy and we might need something smarter in the vsetvli removal pass to detect unneeded changes of the tail policy for instructions that don't care.
Got it, assuming `ta` is more common make sense to me.


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  https://reviews.llvm.org/D93878/new/

https://reviews.llvm.org/D93878