[PATCH] D93878: [RISCV] Don't use tail agnostic policy on instructions where destination is tied to source

[Zakk Chen via Phabricator via llvm-commits]

khchen added inline comments.


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Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:2151
+  bool TailAgnostic = true;
+  if (MI.isRegTiedToUseOperand(0) && !WritesElement0)
+    TailAgnostic = false;
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If the tail policy is ignored on WritesElement0 instructions, why not set tail policy as `tu`? 
Is it because spec said `If anything, the default should be tail-agnostic/mask-agnostic, so software has to specify when it cares about the non-participating elements`?

If we set anything as `tu` except undefined maskedoff, could it also make vsetvli removal easier.




Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D93878/new/

https://reviews.llvm.org/D93878