[PATCH] D93852: [RISCV] Fill out basic integer RVV ISel patterns

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


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Comment at: llvm/test/CodeGen/RISCV/rvv/vand-sdnode-rv32.ll:30
+; CHECK-NEXT:    vsetvli a0, zero, e8,mf8,ta,mu
+; CHECK-NEXT:    vand.vi v16, v16, -1
+; CHECK-NEXT:    ret
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Should we pick a different value here so this test doesn't break if someone fixes DAG combine to optimize out and with -1 on scalable vectors.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D93852/new/

https://reviews.llvm.org/D93852