[PATCH] D93707: [FPEnv] Allow fneg + strict_fsub -> strict_fadd in DAGCombiner

[Nemanja Ivanovic via Phabricator via llvm-commits]

nemanjai added inline comments.


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Comment at: llvm/test/CodeGen/PowerPC/vector-constrained-fp-intrinsics.ll:1062
 define <1 x float> @constrained_vector_fsub_v1f32() #0 {
+; PC64LE:       # float -1
 ; PC64LE-LABEL: constrained_vector_fsub_v1f32:
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RKSimon wrote:
> Was this added by update_llc_test_checks.py ? I'm worried if someone comes along and regenerates it we'll lose this line - what about moving it above the define (update_llc_test_checks.py shouldn't touch it then).
The equivalent of this can be achieved by adding a RUN line with `-mcpu=pwr10` (or a respective target feature attribute for these specific functions). On Power10, we have instructions for materializing floating point constants in registers rather than loading from the constant pool.


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CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D93707/new/

https://reviews.llvm.org/D93707