[PATCH] D93849: [RISCV] Define vmclr.m/vmset.m intrinsics.

[Zakk Chen via Phabricator via llvm-commits]

khchen updated this revision to Diff 313836.
khchen added a comment.

Address frasercrmck's comments, thanks!

I did this way jsut because I think PseduoInst should be expanded after RA
which can ensure source and dest use the same register(non-SSA). I didn't
consider the pros/cons yet.
Could you please share me is there any target also expand PsedoInst in the
ISel custom inserter? I'm wondering that in order to get more precise schedule info,
it means ideally any target would prefer expand pseudo as early as possible.
Maybe the another way is adding schedule info for those pseudo insts?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D93849/new/

https://reviews.llvm.org/D93849

Files:
  llvm/include/llvm/IR/IntrinsicsRISCV.td
  llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp
  llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
  llvm/test/CodeGen/RISCV/rvv/vmclr-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vmclr-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vmset-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vmset-rv64.ll

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