[PATCH] D93809: [RISCV] Add intrinsics for vcompress instruction

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


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Comment at: llvm/test/CodeGen/RISCV/rvv/vcompress-rv32.ll:13
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e8,mf8,ta,mu
+; CHECK-NEXT:    vcompress.vm v16, v17, v0
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Based on the way this intrinsic is defined, this can't be tail agnostic can it?


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D93809/new/

https://reviews.llvm.org/D93809