[PATCH] D93849: [RISCV] Define vmclr.m/vmset.m intrinsics.

[Zakk Chen via Phabricator via llvm-commits]

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Define vmclr.m/vmset.m intrinsics and lower to vmxor.mm/vmxnor.mm.

Ideally all rvv pseudo instructions could be implemented in C header,
but those two instructions don't take an input, codegen can not guarantee
that the source register becomes the same as the destination.

I define two pseduo insts, one would expand to vsetvli + pseduo-v-inst,
then pseudo-v-inst would expand to corresponding v-inst.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D93849

Files:
  llvm/include/llvm/IR/IntrinsicsRISCV.td
  llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp
  llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
  llvm/test/CodeGen/RISCV/rvv/vmclr-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vmclr-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vmset-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vmset-rv64.ll

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