[PATCH] D93599: [DAG] Simplify OR(X,SHL(Y,BW/2)) eq/ne 0/-1 'all/any-of' style patterns

[Bing Yu via Phabricator via llvm-commits]

yubing added inline comments.


================
Comment at: llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp:3979-3980
+              DAG.getNode(ISD::AND, dl, OpVT, RHS.getOperand(0), LowerBits);
+          SDValue NewN0 = DAG.getNode(CmpZero ? ISD::OR : ISD::AND, dl, OpVT,
+                                      LHS, UpperMask);
+          SDValue NewN1 = CmpZero ? DAG.getConstant(0, dl, OpVT) : LowerBits;
----------------
RKSimon wrote:
> yubing wrote:
> > Hi, Simon. It seems that following combine is incorrect?
> > t16: i1 = setcc t34, Constant:i64<-1>, seteq:ch
> > t34: i64 = or t30, t33
> > t33: i64 = shl t31, Constant:i8<32>
> > into:
> > t35: i64 = Constant<4294967295>
> > t36: i64 = and t31, Constant:i64<4294967295>
> > t37: i64 = and t30, t36
> > t38: i1 = setcc t37, Constant:i64<4294967295>, seteq:ch
> > 
> > Before combine, t16 is equal to or(x,shl(y,32)) == -1(i64)
> > But aftercombine, t38 is equal to and(x_low, y_low) ==-1(i32)
> > 
> > This happens in allones_v64i8_and4 with core-avx2
> > 
> I'm sorry but I'm not clear what issue you're saying I've missed in allones_v64i8_and4? Being able to reduce the allbits comparison from i64 to i32 is what we're trying to accomplish. 
> 
> We check that 'x' (LHS) is zero in the upper bits, so we know the upper half of the compare bits come from 'y_low' and the lower half from 'x_low'.
Ah, sorry, I should have seen we check if upper half of x is zero.



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https://reviews.llvm.org/D93599