[PATCH] D92296: [AARCH64] Improve accumulator forwarding for Cortex-A57 model

[Usman Nadeem via Phabricator via llvm-commits]

mnadeem marked an inline comment as done.
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@evgeny777 Regarding the PMUL latency the optimization guide says this. AArch64SchedA57.td probably has older latencies. Should these be updated?

> Cortex-A57 r1p0 and later reduce the latency of ASIMD multiply and multiply-with-accumulate instructions relative to r0pX.

@dmgreen You are correct the only MUL forwarding is from FP MUL (FMUL/FNMUL) and ASIMD FP MUL (FMUL/FMULX). Let me correct that and divide the patch into two.

I'll have to see if there is any negative performance impact first.


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https://reviews.llvm.org/D92296