[llvm] c4ca108 - [SLP] use switch to improve readability; NFC

[Sanjay Patel via llvm-commits]

Author: Sanjay Patel
Date: 2020-12-26T10:59:45-05:00
New Revision: c4ca108966926871a7e2bf362b1816be88a99162

URL: https://github.com/llvm/llvm-project/commit/c4ca108966926871a7e2bf362b1816be88a99162
DIFF: https://github.com/llvm/llvm-project/commit/c4ca108966926871a7e2bf362b1816be88a99162.diff

LOG: [SLP] use switch to improve readability; NFC

This will get more complicated when we handle intrinsics like maxnum.

Added: 
    

Modified: 
    llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp

Removed: 
    


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diff  --git a/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp b/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
index f3a0baa00267..bba6ddc87afb 100644
--- a/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
+++ b/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
@@ -6475,15 +6475,20 @@ class HorizontalReduction {
 
     /// Checks if the reduction operation can be vectorized.
     bool isVectorizable() const {
-      // We currently only support add/mul/logical && min/max reductions.
-      return ((Kind == RK_Arithmetic &&
-               (Opcode == Instruction::Add || Opcode == Instruction::FAdd ||
-                Opcode == Instruction::Mul || Opcode == Instruction::FMul ||
-                Opcode == Instruction::And || Opcode == Instruction::Or ||
-                Opcode == Instruction::Xor)) ||
-              (Opcode == Instruction::ICmp &&
-               (Kind == RK_SMin || Kind == RK_SMax ||
-                Kind == RK_UMin || Kind == RK_UMax)));
+      switch (Kind) {
+      case RK_Arithmetic:
+        return Opcode == Instruction::Add || Opcode == Instruction::FAdd ||
+               Opcode == Instruction::Mul || Opcode == Instruction::FMul ||
+               Opcode == Instruction::And || Opcode == Instruction::Or ||
+               Opcode == Instruction::Xor;
+      case RK_SMin:
+      case RK_SMax:
+      case RK_UMin:
+      case RK_UMax:
+        return Opcode == Instruction::ICmp;
+      default:
+        return false;
+      }
     }
 
     /// Creates reduction operation with the current opcode.