[PATCH] D93705: [RISCV] Define vector mask-register logical intrinsics.

[Zakk Chen via Phabricator via llvm-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rG351c216f36af: [RISCV] Define vector mask-register logical intrinsics. (authored by khchen).

Changed prior to commit:
  https://reviews.llvm.org/D93705?vs=313705&id=313707#toc

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D93705/new/

https://reviews.llvm.org/D93705

Files:
  llvm/include/llvm/IR/IntrinsicsRISCV.td
  llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
  llvm/test/CodeGen/RISCV/rvv/vmand-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vmand-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vmandnot-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vmandnot-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vmnand-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vmnand-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vmnor-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vmnor-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vmor-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vmor-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vmornot-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vmornot-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vmxnor-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vmxnor-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vmxor-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vmxor-rv64.ll

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