[PATCH] D93782: [AMDGPU] Fix adjustWritemask subreg handling
Stanislav Mekhanoshin via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Wed Dec 23 14:24:26 PST 2020
rampitec created this revision.
rampitec added reviewers: arsenm, dstuttard, kzhuravl.
Herald added subscribers: kerbowa, hiraditya, t-tye, tpr, yaxunl, nhaehnle, jvesely.
rampitec requested review of this revision.
Herald added a subscriber: wdng.
Herald added a project: LLVM.
If we happen to extract a non-dword subreg that breaks the
logic of the function and it may shrink the dmask because
it does not recognize the use of a lane(s).
This bug is next to impossible to trigger with the current
lowering in the BE, but it breaks in one of my future patches.
https://reviews.llvm.org/D93782
Files:
llvm/lib/Target/AMDGPU/SIISelLowering.cpp
Index: llvm/lib/Target/AMDGPU/SIISelLowering.cpp
===================================================================
--- llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+++ llvm/lib/Target/AMDGPU/SIISelLowering.cpp
@@ -10862,7 +10862,7 @@
/// Helper function for adjustWritemask
static unsigned SubIdx2Lane(unsigned Idx) {
switch (Idx) {
- default: return 0;
+ default: return ~0u;
case AMDGPU::sub0: return 0;
case AMDGPU::sub1: return 1;
case AMDGPU::sub2: return 2;
@@ -10922,6 +10922,8 @@
// in OldDmask, so it can be any of X,Y,Z,W; Lane==1 is the second bit
// set, etc.
Lane = SubIdx2Lane(I->getConstantOperandVal(1));
+ if (Lane == ~0u)
+ return Node;
// Check if the use is for the TFE/LWE generated result at VGPRn+1.
if (UsesTFC && Lane == TFCLane) {
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