[PATCH] D93791: [AArch64] Add Fujitsu A64FX scheduling model

[Dave Green via Phabricator via llvm-commits]

dmgreen added inline comments.


================
Comment at: llvm/lib/Target/AArch64/AArch64SchedA64FX.td:102
+
+def A64FXAny : ProcResGroup<[A64FXIPFLA, A64FXIPPR, A64FXIPEXA, A64FXIPFLB,
+                             A64FXIPEXB, A64FXIPEAGA, A64FXIPEAGB, A64FXIPBR]> {
----------------
Is this used anywhere? If so, for what?


================
Comment at: llvm/lib/Target/AArch64/AArch64Schedule.td:35
 def WriteID64      : SchedWrite; // 64-bit Divide
+def WriteID512     : SchedWrite; // 512-bit Divide
 def ReadID         : SchedRead;  // 32/64-bit Divide
----------------
What is this for? It doesn't appear to be used in any instructions.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D93791/new/

https://reviews.llvm.org/D93791