[PATCH] D93317: [LV] Vectorize (some) early and multiple exit loops

[Florian Hahn via Phabricator via llvm-commits]

fhahn added a comment.

In D93317#2468673 <https://reviews.llvm.org/D93317#2468673>, @reames wrote:

> Incorporate a fix for the issue Florian found.  Essentially, we can't both treat single use exit conditions as dead, and allow predication to use them in a mask.  Since we know they're evaluate to true for the entire vector body, we can simply ignore them when forming edge predicates.
>
> Florian, any other edge cases you can think of?  I'd completely missed that one.  Thank you for finding it!

I think there are some scenarios when we break some  LCSSA PHIs that use PHIs created  during SCEV expansion when we generate the runtime checks. After a first glance, it appears like an issue after we  add the conditional branch from the `middle` block. The example below should cause a verifier failure with `opt -loop-vectorize -force-vector-width=4`. I tried to reduce it a bit, but unfortunately it is still quite ugly.

  define void @widget(i16** %arg, i64 %N) local_unnamed_addr {
  bb:
    br label %bb1
  
  bb1:                                              ; preds = %bb16, %bb1, %bb
    %tmp = load i16*, i16** %arg, align 8
    %tmp2 = load i16*, i16** %arg, align 8
    br i1 undef, label %bb1, label %bb3
  
  bb3:                                              ; preds = %bb15, %bb1
    br i1 undef, label %bb16, label %bb4
  
  bb4:                                              ; preds = %bb3
    br i1 undef, label %bb5, label %bb15
  
  bb5:                                              ; preds = %bb9, %bb4
    %tmp6 = phi i64 [ %tmp7, %bb9 ], [ %N, %bb4 ]
    %tmp7 = add nsw i64 %tmp6, -1
    %tmp8 = icmp sgt i64 %tmp6, 1
    br i1 %tmp8, label %bb9, label %bb13
  
  bb9:                                              ; preds = %bb5
    %tmp10 = getelementptr inbounds i16, i16* %tmp2, i64 %tmp7
    %tmp11 = load i16, i16* %tmp10, align 2
    %tmp12 = getelementptr inbounds i16, i16* %tmp, i64 0
    store i16 %tmp11, i16* %tmp12, align 2
    br label %bb5
  
  bb13:                                             ; preds = %bb15, %bb5
    %tmp14 = load i16, i16* %tmp, align 2
    ret void
  
  bb15:                                             ; preds = %bb4
    br i1 undef, label %bb13, label %bb3
  
  bb16:                                             ; preds = %bb3
    br label %bb1
  }


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D93317/new/

https://reviews.llvm.org/D93317