[PATCH] D93312: [RISCV] Add ISel support for RVV vector/scalar forms

[Fraser Cormack via Phabricator via llvm-commits]

frasercrmck marked 4 inline comments as done.
frasercrmck added inline comments.


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Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td:417
+                              vti.Vector, vti.Vector, XLenVT, vti.Mask, vti.SEW,
+                              vti.LMul, vti.RegClass, vti.RegClass, ImmType>;
+  }
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frasercrmck wrote:
> craig.topper wrote:
> > This might not catch all immediates it could. The operand of the splat_vector is going to be XLenVT. When the scalar element type is less than XLenVT, only some of the bits of the splat_vector operand are going to be used so the other bits should be ignored for the purposes of checking if the immediate is simm5. We might get lucky because DAGTypeLegalizer::PromoteIntRes_Constant prefers sign_extend.
> That's a good point. I do think `PromoteIntRes_Constant` is saving us here. Is this something that we should fix without a test case, or something to note for later?
Is this something we can leave for a later patch, now that we've got `selectVSplat` and friends which can handle it relatively simply?


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  https://reviews.llvm.org/D93312/new/

https://reviews.llvm.org/D93312