[PATCH] D93705: [RISCV] Define vector mask-register logical intrinsics.

[Hsiangkai Wang via Phabricator via llvm-commits]

HsiangKai added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td:192
+  def : MTypeInfo<vbool2_t, 8, V_M4>;
+  def : MTypeInfo<vbool1_t, 8, V_M1>;
+}
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craig.topper wrote:
> This line has M8 in our downstream repo.
Is it reasonable to change the list as
```
defset list<MTypeInfo> AllMasks = {
  // vbool<n>_t, <n> = SEW/LMUL.
  def : MTypeInfo<vbool64_t, 8, V_MF8>;
  def : MTypeInfo<vbool32_t, 8, V_MF4>;
  def : MTypeInfo<vbool16_t, 8, V_MF2>;
  def : MTypeInfo<vbool8_t, 8, V_M1>;
  def : MTypeInfo<vbool4_t, 8, V_M2>;
  def : MTypeInfo<vbool2_t, 8, V_M4>;
  def : MTypeInfo<vbool1_t, 8, V_M8>;
}
```
If we could do in this way, SEW is redundant. We could set it to constant 8 in the patterns.

For mask logical operations, the important thing is the ratio of SEW/LMUL. If we could keep the relation of vbool<n>_t and the ratio correct, SEW should be not matter.


Repository:
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  https://reviews.llvm.org/D93705/new/

https://reviews.llvm.org/D93705